| Samsung and Cadence Deliver 20-nm Digital Design Methodology |
June 5, 2012 -- Cadence Design Systems, Inc. today announced that Samsung Electronics and Cadence have collaborated to deliver a 20-nm design methodology that incorporates double-patterning technology for joint customer deployment and int ... read more |
| Sonics and Arasan Collaborate on End-to-End IP Subsystems for Mobile Market |
June 5, 2012 -- Sonics, Inc. and Arasan Chip Systems, Inc. today announced a joint agreement to provide SOC designers with end-to-end IP subsystems for today's most popular mobile devices.
The companies wi ... read more |
| ProximusDA Announces ProximusRealizer for Hardware and Software SOC Development |
June 5, 2012 -- ProximusDA GmbH is demonstrating ProximusRealizer, a system-level product that simplifies and accelerates the design and verification of complex systems-on-chip (SOCs). ProximusRealizer helps system and semiconductor compa ... read more |
| Agilent Technologies Accelerates Early Wireless Design Verification with New Release of SystemVue |
June 5, 2012 -- Agilent Technologies, Inc. today announced a new release of SystemVue, Agilent's premier platform for designing communications systems.
SystemVue 2012.06 provides deeper design-flow integration of bas ... read more |
| Hitachi Employs Mentor Graphics' Olympus-SoC Place-and-Route Platform for Critical ASIC Designs |
June 5, 2012 -- Mentor Graphics Corp. today announced that Hitachi, Ltd. has adopted Olympus-SoC place-and-route for large scale ASIC development, and has achieved successful tape out of a 40-nm, 90-million gate design. The Olympus-SoC pl ... read more |
| S2C Releases New Prototype-Ready ARM11 and ARM9 Modules for FPGA-Based Prototypes |
June 4, 2012 -- S2C, Inc. has added ARM1176 and ARM926 GUC test chip modules to its family of Prototype Ready accessories used to create FPGA-based prototypes and to interface FPGA-based prototype boards to the user's target operating env ... read more |
| GlobalFoundries Silicon Validates 28-nm AMS Production Design; Reveals Digital and AMS Support for Double Patterning at 20nm |
June 4, 2012 -- GlobalFoundries is demonstrating an enhanced silicon-validated design flow for its 28-nm Super Low Power (SLP) technology with Gate First High-k Metal Gate (HKMG) at the Design Automation Conference (DAC) in San Francis ... read more |
| Vanguard International Semiconductor Adopts Sagantec Migration Solution |
June 4, 2012 -- Sagantec, Inc. today announced that Vanguard International Semiconductor Corp (VIS) has adopted Sagantec's process migration solution for its standard cell libraries to be able to quickly migrate its IP or modify it to ... read more |
| Northwest Logic Uses Blue Pearl Software's Analyze to Maximize IP Core Quality |
June 4, 2012 -- Blue Pearl Software, Inc. has announced that Northwest Logic, Inc. uses Blue Pearl's Analyze to maximize the quality of its IP cores.
"We have been using Blue Pearl's Analyze for several years and fou ... read more |
| X-FAB Completes Noble Metal MEMS Facility with In-House Gold Processing |
June 4, 2012 -- X-FAB Silicon Foundries AG today announced two major MEMS milestones: completion of its dedicated noble metal facility for MEMS and post-CMOS processing, and shipment of its billionth MEMS device.
The ... read more |
| Timing Closure Experts Launch New Company, Announce Proven Timing Constraints Platform |
June 4, 2012 -- A new electronic design automation (EDA) company and a new product were launched at DAC 2012. Ausdia, Inc. delivers a comprehensive timing-constraints development, verification and management solution that complements all ... read more |
| Mentor Graphics Receives Certification for TSMC 20-nm Process |
June 4, 2012 -- Mentor Graphics Corp. today announced that its Calibre physical verification platform is available for TSMC's 20-nm manufacturing process. TSMC has given Phase I Certification to Mentor's Calibre, certifying it for ... read more |
| Concept Engineering Adds Support for Cadence Virtuoso Spectre to Its Visualization and Debugging Tools |
June 4, 2012 -- Concept Engineering GmbH is adding Cadence Virtuoso Spectre netlist support to its mixed-signal visualization and debugging tools, StarVision PRO, SpiceVision PRO and SGvision PRO. Adding support for another leading simula ... read more |
| Concept Engineering's Nlview Schematic Visualization Engine to Power the Stylus Cockpit for Tabula's Spacetime 3D Architecture |
June 4, 2012 -- Tabula, Inc., a fabless semiconductor company developing 3D programmable logic devices (3PLD), is using Concept Engineering's Nlview automatic schematic generation and viewing engine to power the Stylus GUI cock ... read more |
| EdXact Demonstrates New Belledonne LPE Flow Qualification Tool |
June 4, 2012 -- EdXact hasy announced the availability of Belledonne for the qualification of LPE (layout parasitics extraction) tools. Belledonne allows providers of PDK (process design kits), CAD tool integrators and designers to accele ... read more |
| GlobalFoundries Qualifying Agilent Technologies' GoldenGate and Momentum Simulators for Its RF CMOS Processes |
June 4, 2012 -- GlobalFoundries today announced support for Agilent's GoldenGate RFIC circuit and Momentum 3D planar electromagnetic (EM) simulators for its 65-nm Low-Power enhanced (LPe) RF CMOS process.
The 65L ... read more |
| Integrand Enables RF IC Design Solution for GlobalFoundries' 40-nm LP Technology |
June 4, 2012 -- Integrand Software, Inc. and GlobalFoundries today announced the availability of a comprehensive solution for RF IC design on GlobalFoundries' 40-nm-LP technology. GlobalFoundries' RF solutions fl ... read more |
| Intrinsic-ID Launches Quiddikey-FLEX Flexible Key-Management IP Core |
June 4, 2012 -- Intrinsic-ID has announceds the immediate availability of its Quiddikey-FLEX IP core. Quiddikey-FLEX targets smartcards, medical, FPGA, government, telecom, automotive, networking and communications as well as the mobile m ... read more |
| IPL Alliance Announces IPL 2.0 and Appoints New Chair for Constraint Working Group |
June 4, 2012 -- The IPL Alliance today announced IPL 2.0, an updated release of the first open standard for interoperable process design kits (iPDKs). The IPL 2.0 reference kit includes an iPDK developer's guide, a sample 40-nm) reference ... read more |
| Chip Path Announces Portals for Analysis and Selection of Advanced FPGA Devices |
June 4, 2012 -- Chip Path Design Systems today announced that it plans to deploy free web-accessible portals for selection of advanced FPGA devices from Altera Corp., Lattice Semiconductor Corp., Microsemi Corp. (Actel), and Xilinx, Inc. ... read more |
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