Publication: EE Times EDA Designline
Contributor: Cadence Design Systems, Inc.
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January 30, 2012 -- This is the second in a series of three articles presenting the "top 10" tips for the successful use of formal analysis on IP and SOC projects. As discussed in the first installment, formal analysis has many strengths as a verification technique, including exhaustive mathematical proofs, discovery of bugs that are hard to find in simulation, and an ability to analyze coverage properties (covers) as well as assertions. The first three tips presented were:
- Tip 1 - Involve designers in property specification and, whenever possible, in formal analysis.
- Tip 2 - Apply formal analysis early in the project so that engineers specifying properties see an immediate pay-off.
- Tip 3 - Leverage all forms of automatic assertions, from basic design checkers through assertion synthesis.
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By Thomas L. Anderson and Joseph Hupcey III. (Anderson is a technical marketing consultant who recently served as Product Management Group Director for Cadence Design Systems, Inc., and Hupcey is Product Management Director, Advanced Verification Systems, Cadence Design Systems, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
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Cadence Design Systems, Inc.
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| | Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, formal verification, Cadence Design Systems, EE Times EDA Designline,
| | 602/37782 1/30/2012 620 88 | |
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