Page loading . . .

  
 Category: Magazine & Journal Articles Online: Article Archive 2012: Wednesday, June 19, 2013
Virtual Platforms and RPB for Faster System Verification  
Publication: Design & Reuse
Contributor: Intel Corp.
 Printer friendly
 E-Mail Item URL

March 22, 2012 -- Virtual platforms (simulation environments of SOCs) is an emerging technology for system verification enabling users development of early qualified verification software. Verification of bulk SOCs such as audio, and video architectures with existing methodologies such as emulators, FPGA, CPLD, etc. takes a long time. Virtual Platforms run much faster and provide good debugging mechanism compared to existing methodologies.

As the size of the SOC grows, a virtual platform might comprise third-party components simulated with different methodologies. Co-simulation comes in place, where components are simulated with various tools running simultaneously. These components exchange information in time steps and control signals. When running verification software stacks on co-simulation platform, higher simulation speed is expected for quick verification or debugging. However it would be limited by the component running at low simulation speed. If the time step information, data and control information from such component could be captured and reused in next simulations/re-simulation, the simulation speed of co-simulation platform would be increased for faster verification and debugging.

This article presents a method for faster co-simulation verification where the signal data and time stamp is captured and re-used in next simulations. This method introduces RPB (record and post block) for capture and reuse of the timestamps, data and control signals.

By Praveen Kondugari. (Kondugari is with Intel Mobile Communications.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Design & Reuse website.

Read more about
Intel Corp.
on SOCcentral.com

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, simulation, simulators, virtual platforms, Design & Reuse, Intel,
602/38200 3/22/2012 455 71
Designer's Mall
4th Of July countdown banner
0.15625



 Search for:
            Site       Current Category  
   Search Options


Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Reducing Power
by Raising the
Level of Abstraction


David Pursley
Director,
Product Marketing
Forte Design Systems

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Summertime and the Livin' Ain't Easy


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL?


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
184.602  0.2353516