March 28, 2012 -- This article describes an ASIP decoder template suitable for multi-standard Viterbi, Turbo and LDPC decoding. We show architecture fitness for WLAN, WiMAX and 3GPPLTE standards, although various other standards can also be mapped, since the architecture is capable of supporting any interleaver pattern and programmable in C.
The ASIP core consists of a SIMD with multiple slots each with their dedicated functionality. Because of their block-based approach and possible parallelization decoding strategy, both Turbo and LDPC were mapped using the same concept. Support for Viterbi decoding is made possible through a dedicated decoding pipeline with radix-4 to boost performance well above the tough throughput and latency requirements of the 802.11n standard. Specific instantiations are made to show the flexibility of the architecture.
For each of these instances, area and throughput is given for a commercial 40-nm G technology, showing to be competitive versus other flexible solutions, while offering some key differentiators in the sense of flexibility, usage and specific mode instantiation.
By F. Naessens, P. Raghavan, L. Van der Perre, and A. Dejonghe. (All the authors are with IMEC, Leuven, Belgium.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Design & Reuse website.
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