April 25, 2012 -- As the resolution and speed of converters has increased, the demand for a more efficient digital-side interface has grown. Currently, analog-to-digital converters (ADCs) are migrating from parallel LVDS (low-voltage differential signaling) and CMOS digital interfaces to a serialized interface called JESD204, developed by (formerly known as the Joint Electron Device Engineering Council).
The JESD204 interface brings this efficiency while offering several advantages over its predecessors in terms of speed, size, and cost. Designs employing JESD204 enjoy the benefits of a faster interface to keep pace with the faster sampling rates of converters. In addition, there is a reduction in pin count, which leads to smaller package sizes and a lower number of trace routes, both of which make board designs much easier and offer lower costs in packaging and board designs.
The standard applies to both analog to digital converters as well as digital-to-analog converters (DACs); however, the focus in this article will be on its application to ADCs.
By Jonathan Harris. (Harris is a product applications engineer in the high-speed converter group at Analog Devices, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times Planet Analog website.
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