April 16, 2012 -- Meeting today's tough power specifications involves advanced low-power design techniques that go well beyond clock gating or other power optimizations automated in synthesis and implementation tools.These advanced techniques require architectural decisions that must be made early in the design flow, introducing two big areas of uncertainty that the designer needs to overcome:
How can I get predictability early in the flow to decide which low-power techniques will actually meet the power specification?
Low-power techniques introduce a new level of complexity, so how can I implement those techniques and verify that I did them correctly, ensuring no bug escapes?
This design article uses a case study to illustrate how these twin uncertainties can be overcome. The authors explain how the design is split into power domains, and they show how to apply the following advanced low-power techniques in turn: multi-supply voltage, power shut-off with state retention, and multi-voltage threshold optimization.
The article discusses the resultant dynamic and leakage power numbers estimated at various stages of the design flow, and it shows the importance of realistic activity vectors to produce accurate power estimation. The article also explains how the techniques are specified in a power-intent file, and how that file is used, along with the design and power-aware simulation and formal-verification tools, to verify the correct implementation of the power architecture.
By Pete Hardee and Buda Leung. (Hardee is Director of Solutions Marketing, responsible for the Low-Power Solution at Cadence Design Systems, Inc. and Leung is a solutions engineer with the Silicon Realization Group at Cadence.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
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