April 26, 2012 -- In order to meet high-performance and low-power requirements, FPGA and ASIC designs often include many separate clock domains. This practice creates clock domain crossings (CDCs), which occur whenever a signal is transferred from a clock domain to another. However, these signals may cause data-corruption issues, only occurring during post-layout verification, because conventional RTL verification techniques cannot detect resynchronization problems.As a consequence, critical bugs may escape the verification process and simulation does not accurately predict asynchronous silicon behavior. To predict these problems and debug a design, the Mentor Graphics CDC analysis tools, 0-In CDC, could be included in your DO-254 design flow.
By Florent Checa. (Checa is with France-based Arion Entreprise.)
This brief introduction has been excerpted from the original copyrighted article.