May 15, 2012 -- As the available gate count in FPGAs continues to grow, with 28-nm devices now in full production, more automation is required in design flows to enable engineers to deal with the increased complexity. In a typical FPGA design flow, engineers start implementation with a register transfer level (RTL) description of the design functions, written (mostly manually) in hardware description languages (HDLs) such as Verilog, VHDL, or System Verilog. The RTL description becomes one of the inputs to logic synthesis, which automates the creation of the actual gate-level circuit structure. To meet performance objectives, designers must also supply the synthesizer with constraints for timing specifications, such as clock rate and delays.

Once the gate-level netlist is created, these constraints will guide the place and route tools in the creation of the physical layout. The challenge, for designers, is to be able to create a set of inputs that allow a design to be synthesized and optimized for the architecture of the target FPGA, while also being able to achieve timing closure. This is usually an iterative process, and can often be a major source of project delays when closure cannot be quickly achieved.

By Mike Demler, Editorial Director, OpenSystems Media