May 31, 2012 -- In packaging applications for cellular electronics devices, the use of flip-chip copper pillar bumps has been expanding due to its better shape, lesser thickness, smaller form factor, better performance and lower power consumption. Foundries and semiconductor manufacturers are actively evaluating this new technology as the chips are becoming complex and size is shrinking day by day which leads to higher pin-count and large interconnect densities which can hamper manufacturability of the bump pad.
This article provides an update on the advantages of copper pillar bumps over conventionally used solder bumps; copper-pillar bump design and layout, fabrication and benefits in flip-chip package assemblies.
By Deepak Sharma, Sachin Kalra, Azeem Hasan, and Rahul Saxena. (The authors are with Freescale Semiconductors, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EDN Magazine website.
