June 15, 2012 -- From cameras and flat-panel TVs to IC chip design and even IC transistor design, 3D is the buzzword these days, and authors aren't always clear about what aspects of 3D they're really covering. I'd like to look at the current state of 3D IC (chip) packaging. In particular, let's look at 3D die-on-die stacking techniques, and a variation called 2.5D die-on-silicon interposer packaging, both of which face their own realities of implementation.
By Michael White. (White is the Senior Product Marketing Manager for Mentor Graphics Corp.'s Calibre physical verification products.)
This brief introduction has been excerpted from the original copyrighted article.