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 Category: Magazine & Journal Articles Online: Article Archive 2012: Monday, May 20, 2013
Power-Aware Emulation Tests Power Islands  
Publication: EE Times EDA Designline
Contributor: Emulation and Verification Engineering (EVE)
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June 4, 2012 --Power has pushed performance out of the spotlight. Yes, speed still matters, and, especially in mobile applications, we haven't yet reached that desktop level of "good enough." So there's more work to do to make mobile devices faster, even as more duties are piled on.

The real game is now at the system level, and this involves software as well as hardware. In particular, the ability to shut off parts of the circuit when not in use has become an important consideration. In fact, there's been something of an attitude shift in some quarters: instead of starting with an "everything on" default, and turning things off when you can, start with an "everything off" assumption and turn on only what you need.

Regardless of which of these angles you take, you end up with power "islands" on the chip that can be on or off, and control of the power state can be set either by hardware or software (either low-level firmware or even an application). This reflects an end-point in the ongoing trajectory away from monolithic power. And it adds new verification challenges, especially at the emulation stage, when an SOC is being validated before the actual chip circuitry may be complete.

 

By Ludovic Larzul. (Larzul is Vice President of Engineering, Emulation and Verification Engineering (EVE).)


This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times EDA Designline website.

Read more about
Emulation and Verification Engineering (EVE)
on SOCcentral.com

Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, emulators, emulation, power analysis, power optimization, low power design, low-power design, EE Times EDA Designline, Emulation and Verification Engineering (EVE)
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