|Publication: EE Times Embedded|
Contributor: Mentor Graphics Corp.
June 12, 2012 -- It's a common refrain heard among embedded software design teams everywhere, when the team manager declares, "We need better system power management from both the hardware and software, but we also need to optimize the design for increased functionality and performance."
So, how can a software designer hope to accomplish such a feat when in order to maximize one side of the equation the other side has to be minimized? You just can't have the best of both worlds.
Interestingly, within embedded multicore system design, unique situations present themselves in which power and performance can complement one another – rather than being in a state of perpetual competition. This article considers one such scenario where a symmetrical multiprocessing (SMP) RTOS, multicore hardware, and power management features combine to facilitate parallel embedded programming. While power-management features of a full-featured RTOS contribute significantly to power-efficient design, this article takes an in-depth look at a thread synchronization mechanism based on hardware-supplied primitives, which guarantees power savings while improving system performance.
By Faheem Sheikh. (Sheikh is senior technical lead in the Embedded Systems Division of Mentor Graphics Corp.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times Embedded website.
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Mentor Graphics Corp.
|Keywords: computer system design, general-purpose computers, special-purpose computers, embedded system design, embedded systems, microprocessors, MPUs, multicore processors, multi-core processors, multithreading, multi-threading, power analysis, power optimization, real-time operating systems, RTOS, EE Times Embedded, Mentor Graphics |
|602/38705 6/12/2012 538 105|