|Publication: EE Times EDA Designline|
Contributor: Nimbic, Inc.
June 18, 2012 -- Three-dimensional integrated circuits (3DIC) are generating increased interest as a way to increase speed and density while reducing power and form factor. System-level integration in package (SiP) has joined system-on-chip (SOC) as one of the primary mechanisms to drive the electronic industry. The challenges to develop 3D-IC technologies, however, are formidable, encompassing supply chains, manufacturing, standardization and design technology.
This article focuses on a fundamental aspect of design technology for 3D ICs: Understanding the electromagnetic behavior of 3D structures and how to model them in practice. It examines novel electromagnetic modeling aspects of 3D ICs, in particular, the use of silicon substrates such as silicon interposer, redistribution layer (RDL) and through-silicon via (TSV). It shows how to model electromagnetic properties of silicon substrates, RDL and TSV, how to capture the physical effects in a full 3D solver, and how to incorporate these models into electromagnetic simulation tools. The article concludes with some examples that illustrate the techniques we have developed.
By Raul Camposano, Swagato Chakraborty, Daniel de Araujo, Dipanjan Gope and James Pingenot. (Camposano is CEO of Nimbic, inc.; Chakraborty is Vice President of Products; de Araujo is Director of Applications; Gope is Vice President of Research and Development; and Pingenot is Senior Design Engineer.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
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|Keywords: ASICs, ASIC design, 3D ICs, 3D chips, stacked ICs, EDA, EDA tools, electronic design automation, EM simulation, Nimbic, EE Times EDA Designline|
|602/38803 6/18/2012 1237 80|