July 17, 2012 -- In today's world of terabit telecommunications systems, advanced chip-to-chip interfaces, and high-bandwidth interconnects, the world of picosecond clocking has been left behind. Today's advanced clocking requires sub-picosecond performance as design engineers strive to shave off every precious femtosecond from the jitter budget. With design cycles becoming more constrained and time-to-market pressures mounting, this is a task that is much easier said than done.
That being the case, there still exist systematic ways to improve jitter. By carefully selecting the right technology and partnering with component vendors that have the correct expertise, it is possible to achieve the ultra-low jitter required in the end system without exhausting one's engineering resources on the clock design. This article will discuss some of the major challenges and highlight considerations that can be used to make the correct design trade-offs and component selection.
By Juan Conchas and Aleksandr Borodulin. (Conchas is Marketing Director for the Clock and Timing Business Unit and Aleksandr Borodulin is an Applications Engineer at Micrel, Inc.)
This brief introduction has been excerpted from the original copyrighted article.