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 Category: Magazine & Journal Articles Online: Article Archive 2012: Monday, May 20, 2013
The Fundamentals of Integrating USB 3.0 IP on an SoC  
Publication: Electronic Design Magazine
Contributor: Synopsys, Inc.
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July 18, 2012 -- This article will help you prepare for the technical challenges associated with integrating a compliant USB 3.0 solution. You'll understand implementation considerations in using USB 3.0 IP, including selecting configurable controller intellectual property (IP) and robust physical-layer (PHY) IP. Finally, we'll get into the challenges and solutions for IP testability, verification, hardware validation, driver implementation, and interoperability testing.

By Eric Huang and Gervais Fong. (Huang is Senior Product Marketing Manager of USB IP at Synopsys, Inc., and Fong is a Senior Product Marketing Manager for mixed-signal PHY IP at Synopsys.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Electronic Design Magazine website.

Read more about
Synopsys, Inc.
on SOCcentral.com

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, IP, intellectual property, cores, Universal Serial Bus, USB, Synopsys, Electronic Design Magazine
602/38882 7/18/2012 859 112


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