|Publication: EE Times Memory Designline|
Contributor: Synopsys, Inc.
July 23, 2012 -- Memory plays an essential role in the functioning of embedded systems. Indeed, embedded memories in system-on-chip (SOC) devices can account for 50% or more of chip area. Implemented using aggressive design rules, embedded memories tend to be more prone to manufacturing defects and field reliability problems than any other core on the chip. To improve yield and reliability in embedded devices, manufacturers need solutions that simplify fault detection, process improvement, and repair at the manufacturing level and in the field while minimizing cost and impact on functionality.
This article will describe embedded memory test solutions, including fault detection in very deep submicron technologies, repair at the manufacturing level, and diagnosis for process improvement and field repair capabilities, that address today's design yield and reliability needs.
By Sandeep Kaushik and Yervant Zorian. (Kaushik is the Senior Product Marketing Manager for the embedded memory test and repair products at Synopsys, Inc. and Zorian is the Chief Architect for embedded test and repair products at Synopsys.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times Memory Designline website.
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|Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, design for manufacturing, design-for-manufacturing, DFM, design for test, design-for-test, DFT, design for yield, design-for-yield, DFY, embedded memory, Synopsys, EE Times Memory Designline|
|602/38976 7/23/2012 924 54|