| Moving to Advanced Reliability Verification by Mentor Graphics Corp. in Tech Design Forum |
September 14, 2012 -- Relentlessly shrinking process nodes and the need to balance increasing functionality with greater power efficiency highlight the importance of reliability verification. On one hand, devices and conductors are shrinking, de ... read more |
| Package Interconnects Can Make or Break Performance by Texas Instruments, Inc. (TI) in Electronic Design Magazine |
September 14, 2012 -- Chip and package designers can select from a bewildering catalog of interconnect technologies. Interconnects between the die and package include traditional wire-bond and flip-chip solder bumps, flip-chip gold-to-gold and c ... read more |
| Critical Tools for 20-nm Design by Synopsys, Inc. in Tech Design Forum |
September 12, 2012 -- The shift to 20-nm processes is expected to halve the area used to put a given function on chip, and to offer designers a choice of either halving the design's power consumption or increasing its performance by up to 35%, o ... read more |
| Why IDEs for Hardware Design Fail by EE Times EDA Designline |
September 11, 2012 -- Hardware designers hate integrated development environments (IDEs), and they have good reasons to do so. Most EDA vendors build IDEs that lock the user in. They force a workflow on the user, limit the number EDA tools that ... read more |
| Successful PCB Grounding with Mixed-signal Chips-Part 2: Design to Minimize Signal-Path Crosstalk by Maxim Integrated Products, Inc. in EDN Magazine |
September 10, 2012 -- When we began this series, we observed that board-level designers often have concerns about the proper way to handle grounding for integrated circuits that have separate analog and digital grounds. Part 1 focused on the bas ... read more |
| Interfacing QDR-II+ Synchronous SRAM with High-Speed FPGAs-Part 1 by Cypress Semiconductor Corp. in EE Times Memory Designline |
September 10, 2012 -- Quad-data-rate synchronous static random access memory (SRAM) is an integral part of next-generation networking equipment operating at higher throughput rates. QDR SRAM offers low latency compared to dynamic random access m ... read more |
| LCD Dot-Matrix Solutions with Ultra-Low-Power MCUs by Texas Instruments, Inc. (TI) in EE Times MCU Designline |
September 19, 2012 -- LCDs are a simple way to improve the user experience in a product. As a result, many ultra-low-power products are beginning to integrate LCDs for additional features and functionality. Low cost and low power solutions are c ... read more |
| How FPGAs, Multicore CPUs, and Graphical Programming Are Changing Embedded Design by National Instruments Corp. in EE Times Embedded |
September 5, 2012 -- Embedded systems consist of hardware and software components designed to perform a specific function, and often have real-time and/or reliability constraints which go far beyond everyday computing. To meet these demands on a ... read more |
| Designing a NVMe-Compliant PCIe SSD by IP-Maker in Chip Estimate Corp. |
September 4, 2012 -- NVM Express is definitely the key technology solution to enable the broad adoption of SSD using the PCIe interface. The remaining question is: how to design a PCIe SSD compliant to the specification?
Drivers ... read more |
| How to Test High-speed Memory with Non-Intrusive Embedded Instruments-Part 1 by ASSET InterTech, Inc. in Test & Measurement World |
September 4, 2012 -- Recent surveys of working engineers in the electronics industry by the International Electronics Manufacturing Initiative (iNEMI) found that testing memory and memory buses on circuit boards is one of the most pressing probl ... read more |
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