| Anti-Fuse Memory Provides Robust, Secure NVM Option by Kilopass Technology, Inc. in EE Times Memory Designline |
July 5, 2012 -- Before discussing the strengths and weaknesses of various NVMs, consider the application of NVM in high-volume consumer electronics SOCs and why engineering teams are giving NVM a more-critical examination. In multime ... read more |
| Prevention, Quality and Other Innovations in Hardware Debug by XtremeEDA Corp. in EE Times EDA Designline |
July 2, 2012 -- Debug represents a major cost to hardware development organizations and a constant source of frustration for engineers. According to a survey commissioned by Mentor Graphics in 2010, verification engineers spend an estimated 32% ... read more |
| Embedded Vision: FPGAs' Next Technology Opportunity by EE Times Militray & Aerospace Highlights |
July 2, 2012 -- What up-and-coming innovation can help you design a system that alerts users to a child struggling in a swimming pool, or to an intruder attempting to enter a residence or business? It's the same technology that can warn drivers ... read more |
| Using Java to Deal with Multicore Programming Complexity: Part 2 - Migrating Legacy C/C++ Code to Java by Atego in EE Times Embedded |
June 27, 2012 -- Part 2 in this three-part series on how embedded developers can more effectively exploit the use of multicore Java details the factors to consider in making a decision to shift from C and C++ to Java, as well as providing some g ... read more |
| Using Java to Deal with Multicore Programming Complexity-Part 3: Using Java with C and C++ for Real-Time Multicore Designs by Atego in EE Times Embedded |
June 27, 2012 -- This final part in a three-part series provides guidelines on how to use the combination of the Java parallel-programming language and traditional sequential C and C++ methodologies to achieve real-time multicore software operat ... read more |
| How-to Guide for On-Chip Memory by Toshiba America Electronic Components, Inc. (TAEC) in Electronics Weekly |
June 26, 2012 -- Developers of system-on-chip (SOC) semiconductor devices need to add larger amounts of memory on chip and to support ever higher data rates. This is particularly true in image processing and communications. What are the options ... read more |
| Software Extends Hardware-in-the-Loop Real-Time Simulation by EE Times Automotive Designline |
June 25, 2012 -- Somewhat similar to automotive development, in the space industry the design, building and testing of planetary rover prototypes is extremely expensive, and system testing typically does not occur until late in the design/ testi ... read more |
| Understanding DDR SDRAM Timing Parameters by Freescale Semiconductor, Inc. in EE Times Memory Designline |
June 25, 2012 -- Many engineers who have ever dealt with DDR SDRAM must have been intrigued by the various timing parameters of the DRAM. This article explains the various timing parameters and its impact on the performance of the DRAM. To begin ... read more |
| ACE'ing the Verification of a Cache-Coherent System Using UVM by Mindspeed Technologies, Inc. in EE Times EDA Designline |
June 25, 2012 -- The AMBA 4 specification for the connection and management of functional blocks in a system-on-chip (SOC) now features Advanced eXtensible Interface (AXI) coherency extensions (ACE) in support of multicore computing. The ACE spe ... read more |
| Using Java to Deal with Multicore Programming Complexity-Part 1: How Java Eases Multicore Hardware Demands on Software by Atego in EE Times Embedded |
June 24, 2012 --Developers of embedded software are being forced to figure out ways to exploit the complexity of multicore platforms with languages and library software not designed for multiprocessor environments. This first part in a series of ... read more |
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