| 20-nm Test Demands New Design-for-Test and Diagnostic Strategies by Synopsys, Inc. in Tech Design Forum |
November 5, 2012 -- The introduction of 20-nm manufacturing processes brings new yield challenges that influence design-for-test (DFT) strategies. At 20nm, defect densities are higher, and there are significant on-chip process variations that af ... read more |
| High-Yield, High-Performance Memory Design by Solido Design Automation, Inc. in EE Times EDA Designline |
November 5, 2012 -- In TSMC 28-nm process and as process nodes scale, achieving target yields can be extremely challenging. Nowhere is this truer than for memory circuits, which aggressively adopt next bleeding-edge process nodes to help meet in ... read more |
| Will LDE Stand Between You and Your Next Smart Device? by Cadence Design Systems, Inc. in Electronic Design Magazine |
October 30, 2012 -- Mobility is the key driver for today's consumer. Successful applications must provide technology integration, high bandwidth, and low power. Compared to 28nm, 20nm potentially provides upwards of 20% improved performance, 30% ... read more |
| Embedded S/W Design Reuse: IDEs Are Rising to the Challenge by Atmel Corp. in EE Times MCU Designline |
October 30, 2012 -- As the processing capability of embedded systems increases, design software plays an increasingly important role in the productivity of the design engineer and, ultimately, the success of the end product. When a design engine ... read more |
| Modeling of Embedded Designs-Part 1: Why Model? by National Instruments Corp. in EE Times Embedded |
October 30, 2012 -- This first part of a four-part tutorial on modeling tools provides a brief introduction to the range of modeling methodologies and why you should consider their use in your embedded designs.
Creating a model ... read more |
| Electrically-Aware Design Improves Analog/Mixed-Signal Productivity by Cadence Design Systems, Inc. in EE Times EDA Designline |
October 29, 2012 -- One of the biggest challenges in analog/ mixed-signal IC design is uncertainty in electrical behavior and reliability. While uncertainty can be a problem at any process node, it is particularly pronounced at the advanced node ... read more |
| ARM-Based Android Hardware/Software Design Using Virtual Prototypes-Part 1: Why Virtualize? by Synopsys, Inc. in EE Times Embedded |
October 27, 2012 -- The Android Software Development Kit (SDK) enables the software community to develop applications that take advantage of the latest handset features before the handset is even available. SDKs are tailored and extended by hand ... read more |
| RTL Analysis for Complex FPGA Designs Using a Grey Cell Methodology by Blue Pearl Software, Inc. in EE Times Programmable Logic Designline |
October 26, 2012 -- As designs are getting more complex, we are seeing two major issues that customers have to deal with in the RTL analysis space.
The first issue has to do with sheer design size and the associated data volume. ... read more |
| Emulation Delivers System-Level Power Verification by Mentor Graphics Corp. in Tech Design Forum |
October 26, 2012 -- Emulation has become the necessary system-level low-power verification and power analysis technique for today's SOCs. It allows engineers to make truly informed decisions based on views of the full chip.
Emul ... read more |
| How Low Power Becomes No Power by Texas Instruments, Inc. (TI) in Electronic Products Magazine |
October 26, 2012 -- Lately, many different microcontrollers tout the lowest power consumption in various modes of operation. Why these modes are chosen and what that means for actual applications can often vary as much as the methods employed to ... read more |
|
