| eWLB As a Cost Effective Platform for 2D–3D Packaging Solutions by STATS ChipPAC, Ltd. in ElectroIQ |
October 1, 2012 -- The market for portable and mobile data-access devices connected to a virtual cloud access point is exploding and driving increased functional convergence as well as increased packaging complexity and sophistication. This arti ... read more |
| The Semiconductor Review September 2012 Update by weSRCH |
September 27, 2012 -- August 2012 for our industry was a quiescent month, but a disconcerting one nonetheless. By its end, the Caris & Company Semiconductor Composite Index had appreciated 2.2%, which was certainly a valuation gain superior to t ... read more |
| Enhancing Verification through a Highly Automated Data Processing Platform by Infineon Technologies AG in Design & Reuse |
September 26, 2012 -- This article discusses a low-cost, portable, reusable, fully automated platform implemented to enhance the verification process. This flexible platform is a VB-based data-processing platform which is able to process and int ... read more |
| Designing a Reset-Aware OVM Testbench by Intel Corp. in EE Times EDA Designline |
September 24, 2012 -- Reset is a state that exists for almost every single IP, and is usually controlled by at least one, in some cases more than one, input signal. Typically, a design starts in the reset state and when the reset signal is deass ... read more |
| How to Test High-speed Memory with Non-Intrusive Embedded Instruments-Part 2 by ASSET InterTech, Inc. in Test & Measurement World |
September 13, 2012 -- Having explained in the first article in this three-part series the nature of the memory test challenge in the industry today, this article discusses non-intrusive debug and test methods based on embedded instruments and ho ... read more |
| Floorplanning: Concept, Challenges and Closure by Freescale Semiconductor, Inc. in EDN Magazine |
September 19, 2012 -- In today's world, there is an ever-increasing demand for SOC speed, performance, and features. Complex integrations and smaller design cycle emphasize the importance of floorplanning, i.e., the first step in netlist-to-GDSI ... read more |
| Audio-Signal Processing without Code Headaches by ECN Magazine |
September 18, 2012 --- It seems few people lack an audio device, which can include an MP3 player and small sound bar up to a custom HiFi sound system in a home theatre. Unknown to the consumers, though, engineers have spent considerable time and ... read more |
| Addressing Memory Performance for 100G Ethernet Networking by Memoir Systems, Inc. in Chip Estimate Corp. |
September 18, 2012 -- 100G Ethernet poses challenges not just to transmission, but also to packet processing, quality of service and rapid routing. Systems designers can crank up processing performance by using multicore processors. However, if ... read more |
| Interfacing QDR-II+ Synchronous SRAM with High-Speed FPGAs-Part 2 by Cypress Semiconductor Corp. in EE Times Memory Designline |
September 17, 2012 -- Implementation of memory interfaces on FPGAs, especially for high-speed memories, was a tedious process until most of the FPGA vendors started providing configurable memory controller IP, such as the Xilinx Memory Interface ... read more |
| Successful PCB Grounding with Mixed-Signal Chips-Part 3: Power Currents and Multiple Mixed-Signal ICs by Maxim Integrated Products, Inc. in EDN Magazine |
September 17, 2012 -- This is the final part of a three-part article in which we consider the power source currents and how to apply what we have learned to circuits with multiple mixed-signal ICs. This part concludes with an example where a gro ... read more |
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