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 Category: SOCcentral Feature Articles & Columns: Barbaras Bytes: Monday, October 24, 2016
So, Just What Is ESL?   Featured
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March 11, 2013 -- The challenges now facing semiconductor companies are huge, and they don't stop with complexity. In tiny geometries, with as many as tens of millions of gates, today's SOCs are likely to be multicore and to have on them up to 100 IP blocks. The clincher, though, is that despite all that complexity, silicon has become almost a commodity with software having become the differentiator.

Indeed, by 2015, it's said that more than half of the total effort in SOC design will go into software. End users are demanding the latest OSs and applications, setting the bar high for OEMs that are relying on semiconductor vendors to deliver working silicon and software in the same package. Semiconductor companies, in turn, are counting on tool vendors for solutions that enable this hardware/ software convergence, creating the need for tools that work at a higher level of abstraction. This scenario has expanded the magnitude of the problem that is chip design today.

Anticipating the need for design above RTL many years ago, Gary Smith of Gary Smith EDA coined the term ESL for electronic system-level design. Originally, Smith envisioned that a single company would offer a full commercial ESL flow. But today Smith concedes that, "The design flow now is so extensive that no one company will ever be able to do the whole job." Hardware/ software co-design has made verification the biggest problem, Smith notes.

Johannes Stahl, Director of Product Marketing for System Level Solutions at Synopsys, Inc., says that we should stop talking about the misnomer of ESL. "Visionaries see a unified flow while pragmatists look at specific disciplines."

It's Stahl's position that we should speak of specific design tasks meaningful to people with jobs. "Pragmatists will spend money to solve problems that are much-more pointed and real to the end user." System architect teams work in their own little worlds, he points out. Though sometimes connected to verification, in most cases they're isolated. They'll get information like power, but organizationally they're very separate. The software team is as separate as you could imagine, says Stahl, "We connect software to hardware."

The need to design and verify silicon and software within a very narrow window and for a single OEM has made today's environment highly competitive. "When the next version of the Android OS becomes available, for example, a semiconductor vendor working on a chip has to test it on the virtual prototype before even thinking of giving silicon to the OEM," notes Stahl. "Software is what stands between the chip and revenue."

Stand up and be noticed

Instead of any one vendor having a unified flow, each vendor has a technology that stands out in the high-level design space. For Synopsys, Inc., that technology is a software virtual prototype dubbed the Virtualizer. Its origins go back to a trio of companies Synopsys acquired: CoWare, VaST and Virtio. The Virtualizer Development Kits (VDKs) are software development kits that use virtual prototypes as the embedded target to accelerate OS bring-up and the development of firmware, device drivers and middleware. Stahl reports that Synopsys either supplies a team to develop VDKs, or customers build a team which could be a hardware or software team. The latest VDK Synopsys announced gives designers a jump-start on software development for SOCs based on ARMv8-based processors.

The foundation of the virtual prototype is transaction-level modeling (TLM) for IP. It took 10 years for SystemC to become mature, recounts Stahl. The models for virtual prototyping don't have enough detail to be used for high-level synthesis (HLS), but they can be used for verification. His advice is to stay close to the actual problem. As for what comes next? "At the architectural level, there's only one way to go, and that's up," says Stahl.

Synopsys is putting a lot of effort into a higher level of modeling that would sit on top of SystemC. "We'd still use transactions," Stahl says. "Think of a video stream, but instead of the content of the video frame, interest would be limited to the arrival time, latency and pipeline." The idea here would be to get to the essence of the information to keep modeling efficient at the performance level, thus creating what Stahl calls "performance models."

While Stahl focuses on design tasks, Shawn McCloud, Vice President of Marketing at Calypto Design Systems, Inc., speaks of sub-flows, some that help with developing a TLM virtual platform for system analysis, such as the Virtualizer, and some that target hardware implementation. That's where Calypto stands out with its HLS and C-to-RTL formal equivalence. Because the top requirement for HLS is the quality of the resulting hardware, the models used for a TLM virtual platform and HLS are typically different. "Eventually, the models will become closer, but I don't see this as a requirement today to adopt ESL," says McCloud.

Calypto's HLS came out of Mentor Graphics Corp. which a year and a half ago merged its ESL group with Calypto and is now a shareholder of that company. What users had known as Mentor's Catapult C product now is Calypto's Catapult HLS tool. McCloud points out that in contrast to the first behavioral-synthesis tools in the mid 90s, which synthesized an RTL abstraction of SystemC but provided very little benefit over RTL, the latest generation of tools similar to Catapult synthesize very abstract, un-timed C++ or SystemC closer to the TLM domain. Catapult now optimizes for power as well as performance and area, and is being integrated with Calypto's sequential logic equivalence checker.

"ESL is an overused term. So many different tools have been thrown into the ESL bucket that don't belong there," notes McCloud, adding that there are two requirements that define ESL: first is designing above RTL, and second is the requirement of at least a 10X productivity gain.

"ESL requires a pretty large abstraction jump and methodology change from writing in purely RTL. The productivity requirement is important because without it, one doesn't have enough benefit to make the jump." Users need to learn how SystemC and C++ blocks can coexist with existing RTL blocks. Calypto finds the typical learning curve to be about six months before a designer can become proficient enough to realize at least a 10X productivity gain. So it's a matter of pain versus a payoff in productivity. "70% of the new hardware design is in the mobile market, and every year there's a new product. You can't do that with RTL," notes McCloud,

Forte Design Systems, Inc. also has an HLS tool. Brett Cline, Vice President of Marketing and Sales at Forte, prefers to refer to behavioral design rather than ESL. "Our job is to allow our users to create and reuse better IP more quickly and with fewer resources. By better, we mean better quality of results area, power and performance. The real win for SystemC synthesis is design re-targeting and reusability. Productivity shoots up to 20X to 30X and sometimes more by reusing technology-independent design implementations and allowing Forte's Cynthesizer HLS tool to re-target the design to a new technology library and clock speed."

Although HLS holds out the promise of productivity gain, Cline says that some users are not so eager to move beyond their existing flows because not everyone is ready to confront the risks required to reap the rewards. But Phil Tharp, principal engineer at Adapt IP (formerly HighIP) is a believer. "We can produce state-of-the-art IP using Forte's Cynthesizer and SystemC. The use of this methodology has allowed us to produce high-quality IP with fewer resources and has the added advantage that we can offer high-level TLM models that are guaranteed accurate,"

There's some truth in every cliche

"The term ESL is hard to get rid of because there's something to it," acknowledges Frank Schirrmeister, Group Director Product Marketing Systems and Software Realization for Cadence Design Systems, Inc. According to his definition, "ESL is everything that happens before RTL is stable."

"People are using specific point flows. It's not a lack of money that keeps some from moving to a higher abstraction level, but they hesitate to invest in something that's so far away from tape-out," says Schirrmeister. And what's the motivator for those who do embrace it? "Some have had failed designs; others want to design better products and to get product to market faster and at lower cost," Schirrmeister reports.

As for target segments adopting design above RTL, it's across the board, he notes. The wireless market is embracing the methodology to make sure it supports the right protocols, the wired market to get partitioning right and the automotive market for software development. "The more you embrace ESL, the more time you shave off the design cycle, especially for derivative designs. Sometimes the benefit isn't visible the first time around," says Schirrmeister.

Figure 1. Today's SOC design flow. Green boxes indicate reused IP, grey boxes show design processes such as high-level synthesis, and orange boxes depict development results such as transaction-level models (TLM) on the hardware side and RTOS on the software side. The flow starts on the left where hardware/software partitioning takes place. Software development occurs at the top and hardware development at the bottom. The integration of hardware and software, shown in the center, starts with virtual prototyping. Source: Cadence Design Systems, Inc.

Cadence's strength in ESL is its acceleration and emulation technology which helps SOC design teams with the challenges of hardware/ software co-verification. With 4-MHz performance, the Palladium XP emulator brings together simulation acceleration and emulation. Its hot-swap technology lets users switch from simulation to simulation acceleration to emulation at run-time. NuFront, a provider of chip sets for mobile computing, used Palladium XP to verify and emulate its third-generation NS115 computer system chip with a laser focus on performance and power plus Android applications. The NS115 is a complex design with a dual-core ARM Cortex-A9 processor plus a graphics processor, hardware-acceleration block, numerous interfaces and memory sub-systems. NuFront found the emulator to be able to synthesize and implement its entire 12-million-gate chip while being about 1,000 times faster than software simulation and achieving up to a 1.3-MHz real-time frequency. Nufront's new chip enables Xusit's seven-inch IPS Tablet.

Users of Cadence's emulator can also integrate high-level abstraction models such as C, C++ and TLM into their system-verification environment with the platform's SystemC-to-emulation flow. "TLM is the next level of design entry," predicts Schirrmeister. Though it's not quite part of the mainstream flow today, he expects TLM to become ubiquitous like RTL. And after that, it's on to the next level where we consider functionality independent of hardware and software. It's Schirrmeister opinion that we'll need MathWorks, Inc.'s MATLAB."

But that's getting ahead of ourselves. While we're waiting for that leap to take place, Atrenta, Inc.'s technology provides a bridge from ESL to implementation. Atrenta's SpyGlass predictive analysis software cleans up the RTL in IP and SOCs. "As much as 70% of an SOC comprises IP being stitched together," says Mike Gianfagna, Atrenta's Vice President of Corporate Marketing. SpyGlass helps to ensure a chip is correct and will function in the system properly before hand-off by determining what the fault coverage will be. Either you can listen to what SpyGlass says, warns Gianfagna, or you can wait until just before tape-out at gate level. Atrenta recently acquired NextOp and its assertion synthesis, giving its customers much needed help with functional verification. "NextOp's assertion synthesis technology now does for verification engineers what SpyGlass does for design engineers," notes Gianfagna.

Gianfagna's vision for the future is to turn things on their head and have software engineers driving hardware teams to use an iterative process that results in hardware that will run software in the most power-efficient way. "That would lead to killer user experiences," notes Gianfagna. A small number of consumer and semiconductor vendors are already doing this, and he says the hardware/ software interface with a focus on power is where the opportunity lies.

It's smart to be thinking of new methodologies since end-user applications will put increased demands on the design of SOCs. For the most part, though, we each need to keep our nose to the grindstone because chip design today is challenging enough. But one thing is indisputable hardware and software are now joined at the hip. We'll have to consider the design of the two ever more closely.

By Barbara C. Tuck.

Barbara Tuck is's Senior Editor for SOC design and all things related to EDA, ASICs and FPGAs, and IP. In addition to her work with SOCcentral, she is available for freelance assignments and can be reached by phone at 843-972-8051 or by e-mail at

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, electronic system level design, electronic system-level design, ESL, SOCcentral,
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