February 22, 2006 -- Axiom Design Automation today announced the availability of CompiledTestbench (CTB), a testbench simulator supporting industry standard OpenVera and SystemVerilog hardware verification languages. CTB can be used as an integral part of Axiom's MPSim verification environment or on a standalone basis with other simulators. MPSim is the only commercially available simulator that leverages multi-processor hardware to accelerate overall verification performance.

CTB enables engineers to create a comprehensive verification methodology using object-oriented programming, advanced data types, constrained-random stimulus, functional coverage and assertions.

While offering a migration path to SystemVerilog, CTB provides extensive support for the OpenVera language enabling designers an easy migration path without requiring any changes to their existing design or methodology. Using CTB, designers have achieved up to 5x performance over interpreted testbench products.