May 8, 2012 -- Cadence Design Systems, Inc. today announced that Fujitsu Semiconductor, Ltd. has adopted the newly updated Cadence Chip Planning System at its nine design centers spread around the globe. Fujitsu Semiconductor chose the Cadence system because of the time, accuracy and cost benefits it offers in the development of its MCU chips requiring large-scale integration (LSI).

"We continue to expand our use of the Cadence Chip Planning System at Fujitsu Semiconductor for one key reason; it helps us build better chips faster," said Mutsuaki Kai, Vice President of Environmental Technology Development and Products Engineering Division, Fujitsu Semiconductor. "The latest enhancements to the technology have increased its value to us, and the combination of the technology and the support from Cadence has made this chip planning system a significant factor in our efforts to stay ahead of our competitors."

The Cadence Chip Planning System enables early and accurate IC estimation, allowing trade-offs between chip size, power consumption, cost, and time-to-market. Newly added features include advanced interactive I/O planning and links to board- and package-design solutions, enabling earlier and more-accurate die size and power estimation. The Cadence technology delivers a unified chip-planning environment that enables efficient information sharing among global design teams.

Leveraging high-fidelity models of semiconductor IP and manufacturing processes, the system provides a unified cockpit for technical and economic chip estimation which can be shared by multiple design teams. With the help of Cadence engineers, Fujitsu Semiconductor design teams further customized and tailored the system to take advantage of several of its unique technologies, enabling even more finely tuned chip plans.