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Thursday, May 23, 2013

MIPS Technologies Introduces New Aptiv Generation of Microprocessor Cores Featured

May 14, 2012 -- MIPS Technologies, Inc. has introduced a new generation of microprocessor cores. The Aptiv Generation cores, including the proAptiv, interAptiv and microAptiv families, offer three distinct performance levels for applications across MIPS' target segments.

All based on the MIPS32 Release 3 architecture, the products are targeted to build on MIPS' position in home entertainment, strengthen its position in networking, extend the company's offering in the high-volume embedded systems segment, and provide a competitive alternative for mobile system development. For mobile devices, the Aptiv Generation offers top-end multicore performance for applications processing in products including tablets and smartphones, efficient multi-threading technology for applications such as baseband processing, and entry-level performance for embedded control and applications such as touchscreen controllers, SIM/security and GPS.

proAptiv family key features

High-end CPU-performance efficiency delivering over 4.4 CoreMark/MHz and 3.5 DMIPS/MHz in considerably smaller area compared to competing IP cores.
Ideal for applications processing in connected consumer electronics such as high-end mobile devices and smart home-entertainment products, and control plane processing in networking applications.
Efficient top-end performance minimizes the need for exotic power management schemes in many mobile applications.
60% to 75% higher performance on CoreMark and DMIPS scores compared to MIPS32 74K/ 1074K superscalar single/ multicore products.
Highly-scalable solution leveraging one or more threads per core, and up to six cores connected in a multicore Coherent Processing System (CPS).
Major architectural features and enhancements
- High-performance multi-issue, deeply out-of-order (OoO) architecture with state-of-the-art branch prediction.
- New higher-performance floating-point unit (FPU) with higher synthesizable frequency for 1:1 clock with core and native double-precision execution.
- Single-core and multicore (up to six core) configurations.
- Performance-enhanced, tightly-integrated second-generation Coherence Manager and L2 cache controller with lower total latency.
- MIPS DSP Application Specific Extension (ASE) v2.
- Enhanced Virtual Address (EVA) for efficient 32-bit address map utilization to reach 3-GByte+ user space.

interAptiv family key features

The interAptiv core leverages a balanced nine-stage pipeline with multi-threading to deliver leading performance efficiency, achieving greater than 50% more CoreMark/MHz than competing cores in similar die area.
Ideal for highly-parallel applications requiring cost and power optimization, such as smart gateways, baseband processing in LTE user equipment and small cells, SSD controllers and automotive equipment.
Highly-scalable solution leveraging one or more threads per core, and up to four cores connected in a multicore Coherent Processing System (CPS).
Features and enhancements
- Multi-threaded pipeline implements dual virtual processors, appearing as two complete CPUs to an SMP Linux operating system.
- Hardware Quality-of-Service (QoS), thread-management support and inter-thread communication enable optimal control for real-time applications.
- Performance-enhanced, tightly-integrated second-generation Coherence Manager and L2 cache controller with lower total latency.
- Support for up to two I/O coherency units.
- Core and CPS-level power-management features.
- Error checking and correction (ECC) support in L1 data cache, L2 cache and data SPRAM.
- Enhanced Virtual Address (EVA) for efficient 32-bit address map utilization to reach 3-GByte+ user space.
- Optional floating-point unit.

microAptiv family key features

Low-power, compact, real-time embedded processor core with integrated standard I/O interfaces, building on MIPS32 M14K core family with microMIPS code compression instruction set architecture.
Integrates DSP and SIMD functionality to address signal-processing requirements for a wide range of embedded segments including industrial control, smart meters, automotive and wired/ wireless communications.
Leverages highly-efficient 5-stage pipeline to achieve 3.09 CoreMark/MHz and 1.57 DMIPS/MHz in microMIPS mode, with 40% and 25% higher performance, respectively.
MCU and MPU (with integrated cache controller/ MMU) product versions available for microcontroller and embedded applications.
Compared to previous generation MIPS cores and competitive cores, offers greater range of design features for both control and DSP operations.
New memory-protection unit for enhanced program code and data security, microMIPS-only execution mode, secure debug and 2-wire cJTAG support.

Availability

All Aptiv core families can be licensed now. The proAptiv family will be generally available in mid-2012 supporting a range of functional and performance points with single and multi-core versions. The new proAptiv FPU is also available. The interAptiv family will be available in mid-2012 in dual- and quad-core configurations, with optional FPU. Single core versions will be available in the fourth quarter. The microAptiv family is available now, with cache/ MMU or non-cached core options.

Go to the MIPS Technologies, Inc. website for details.

E-mail MIPS Technologies, Inc. for more information.

Read more about
MIPS Technologies, Inc.
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Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, IP, intellectual property, cores, microprocessors, MPUs, multicore processors, multi-core processors, MIPS Technologies, Aptiv, proAptiv, interAptiv, microAptiv

601/38431 5/14/2012 441 64

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