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AMD Selects Synopsys As a Verification IP Partner to Further Accelerate SOC Verification  
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May 14, 2012 -- Synopsys, Inc. today announced a multi-year agreement to provide Advanced Micro Devices, Inc. (AMD) with its next-generation Discovery Verification IP (VIP). Based on the new VIPER architecture, the recently announced Discovery VIP family provides inherent performance, ease-of-use and extensibility to speed and simplify verification of the most complex system-on-chip (SOC) designs. This agreement covers a variety of VIP titles including USB 3.0, ARM AMBA AXI interconnect, SATA 3.0, PCI Express Gen 3, and MIPI, as well as Synopsys' Protocol Analyzer, a protocol-aware SOC debug environment.

"In our verification environment for Southbridge SOCs and IP cores, we utilize several interfaces, including AXI3 and USB 3.0. After an extensive evaluation, we selected Synopsys' next-generation Discovery VIP for several of our leading SOC designs,"" said Thomas Bodmer, Manager of Design Engineering at AMD. "With Discovery VIP, we have seen benefits in minimizing our simulation runs and achieving higher coverage. We have used Synopsys' Protocol Analyzer technology to narrow down protocol violations and debug the root causes."



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Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, verification IP, intellectual property, cores, Synopsys,
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