July 9, 2012 -- Synopsys, Inc. today announced that its PCI Express controller IP with support for low-power sub-states has successfully taped out in multiple designs. The addition of the L1.1 (snooze) and L1.2 (off) sub-states to the DesignWare controller IP for PCI Express 1.0, 2.0 and 3.0 enables designers to reduce power consumption in key market segments, including camera, card reader, networking and wireless applications serving the ultrabook and tablet markets. L1 sub-states reduce a PCI Express system's link idle power consumption from 15mW to 20mW per lane to 10µW per lane, or by approximately 99%, by re-purposing the signals between the PHY and the controller so that they turn off the high-speed circuits in the PHY when not in use.

Reducing standby power is a prerequisite for the emerging thin- and light-form-factor mobile markets, and has now become critical in multiple market segments that must meet stringent regulatory power requirements such as European Regulation 1275/2008. To address these requirements, PCI-SIG members, including Synopsys, are proposing L1 sub-states to supplement previously adopted power-saving features such as Latency Tolerance Reporting (LTR) and Optimized Buffer Flush/Fill (OBFF). Synopsys' support for L1 sub-states has already enabled market leaders to integrate this new power-saving technology into ten designs while maintaining backward compatibility with existing PCI Express devices. With first silicon back on several of these designs, adopters are well on their way to delivering their low-power mobile products on or ahead of schedule.

Availability

Synopsys DesignWare controller IP for PCI Express with support for L1 sub-states is available now. The L1 sub-state engineering change request (ECR) is in the final stages of becoming an engineering change notification (ECN) to the PCI Express specification.

Posted by: John Miklosz