System-on-chip (SoC) architectures integrate several processing units on a single die. With every passing generation, the need for enhanced processing power vis-à-vis higher system complexity has resulted in an increase in the number of processing engines that are integrated on the chip. While designs with tens of processing engines are already in production, next generation SoCs will easily integrate hundreds of processing cores. SoC architectures can be broadly classified into symmetric multi-processor architectures (SMP) such as those used in the MIT RAW project, and asymmetric application specific architectures that are widely used in targeted application domains such as high definition video decoders. The complexity of on-chip communication between the processing engines of a SoC has led to several innovations in the communication architecture design and synthesis.
