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A Flexible Solution for Implementing Structured ASIC Designs   Featured
Contributor: Magma Design Automation, Inc.
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August 28, 2006 -- Compared with FPGAs, structured ASICs provide more performance, lower per-unit cost and lower power consumption. This device class operates much like an application-specific ASIC or FPGA, using pre-diffused blocks coupled with a large number of logic "tiles" that can be configured by a few metal layers to add the custom logic. This capability significantly decreases the risks associated with designing high performance, cost-effective chips by shortening design time because the logic is already diffused and often has lower-level interconnect and clock trees already implemented. Structured ASICs also use fewer design masks compared to standard cell ASICs, dramatically reducing fixed non-recurring engineering (NRE) costs and manufacturing turnaround time.

As a result, structured ASICs are becoming the popular choice for large devices numbering 10,000 to 100,000 units. There have been some key problems delaying adoption, however, namely significant differences in implementing design flows.

Figure 1. A typical structured ASIC floorplan.

These differences highlight the fundamental problem of structured ASIC design – the design tools. Many design tools have evolved from the traditional ASIC approach, which calls for an open floorplan with fine grained architectures resembling traditional high-end gate array devices. These tools handle issues such as timing closure, routing and signal integrity well, and add scan chains for testing, but they don’t work well with the fixed floorplan or coarser-grained architectures of other structured ASICs.

On the other hand, structured ASICs using tiles with multiplexers or lookup tables (LUTs) combined with register elements are more easily handled by FPGA design tools. But these often lack the sophisticated signal integrity, routing and timing capabilities needed to get the best performance out of the structured array. The ability to handle and place many different types of blocks with global and local routing, clock tree synthesis, parasitic extraction, and design for test (DFT) and design for manufacturability (DFM) elements, is vital to complete structured ASIC designs. This capability is not common in FPGA-type tools.

It's possible to use either type of tool (ASIC or FPGA) for designing a structured ASIC, but the difference is the cost of the end device. The fine-grained architectures have better utilization so a design can fit into a smaller device, reducing the cost. When shipping hundreds of thousands of devices, a few cents makes a substantial difference. But this comes at a cost – more connections, more routing congestion, larger interconnect delays and, as a result, lower performance.

The medium-grained architectures have more efficient connectivity but give lower logic utilization and, consequently, a larger die with higher costs. To further complicate matters, some applications may be better suited to a fine-grained architecture, while others map better onto a medium-grained array.

What is needed is a solution that can work efficiently across both fine-grained and medium-grained architectures, accepting multiple levels of hierarchy and including high-end ASIC capabilities such as heterogeneous placement, clock tree synthesis and signal integrity issues, to produce the smallest die size for a given performance.

A complete design implementation solution

Magma’s Blast Create SA and Blast Fusion SA provide such a solution for structured ASIC design implementation. Blast Create SA automatically imports all the structured ASIC logic and physical cell libraries to create a fixed floorplan that drives the whole implementation process. The synthesis engine incorporates Boolean matching and mapping to LUTs or multiplexers for each of the different types of architecture, and uses any on-chip buffers and dedicated cell drivers to meet the timing constraints.

The tool also handles physical synthesis, with detailed knowledge of each of the structured ASIC target architectures such as physical layout and routing models. Unlike traditional ASIC tools, however, Blast Create SA takes full advantage of the tile structures and hierarchy throughout the whole device, mapping the design into the optimum number of tiles and using the spare resources in each tile to reduce the routing complexity, increase the performance or reduce the die area.

Also, unlike conventional FPGA-based synthesis tools where the packing algorithms are typically limited to one or two LUTs or multiplexers and registers in a logic element, Blast Create SA is capable of packing throughout the hierarchy from basic tiles to clusters of tiles and master tiles.

Blast Fusion SA moves the design from netlist to GDSII for production using a physically-aware optimization algorithm to take full advantage of the tile structures. These placement and routing technologies have new algorithms that take into account the complex constraints that are inherent in the pre-defined routing of structured ASICs (Figure 2).

Figure 2. Fully placed and routed design using Magma Blast Fusion SA.

Like Blast Create SA, all of Blast Fusion SA’s implementation and analysis engines have immediate and concurrent access to a unified data model, which allows for modifications on the fly and a manufacturable design generated in the shortest possible time while still hitting performance and cost targets.

To enable these capabilities, Magma works with all the leading structured ASIC vendors to include their architectures in the implementation flow and ensure that the tools are aware of the variations in the different architectures.


Structured ASICs provide the ability to cost-effectively manufacture high-performance designs in medium to high volume with substantially lower NRE costs than ASICs and substantially lower per-unit costs than FPGAs. But getting the best performance with the smallest die area out of the many different technologies and design tools has been difficult, so optimized versions of ASIC tools are needed to provide a complete, unified RTL to GDSII design flow for the wide range of structured ASIC architectures.

By Sanjay Bali. Product Director, Design Implementation Business Unit, Magma Design Automation, Inc.

Go to the Magma Design Automation, Inc. website to learn more.

Keywords: SOCcentral, Magma Design Automation, structured ASICs,
488/19928 8/28/2006 5254 5254
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