It’s no surprise—design houses want their designs to attain the best yields possible from the foundry. To that end, many design-for-manufacturing (DFM) techniques have been adopted during the design and verification flows to minimize process variability and ensure manufacturability. But DFM only helps if it’s used.
When designs include external intellectual property (IP), as they often do these days, it’s not always the case that the IP has gone through the same rigorous DFM analysis and optimization that the rest of the design has. That can create manufacturing issues over which the chip designer has no control, a scary feeling when profits and market share are at risk.
IP customers expect and demand that the IP has also been optimized with the latest DFM technologies to ensure production quality and consistency are maintained throughout the design. Unfortunately, not all IP vendors invest the time and money needed to ensure that their IP is in compliance with DFM criteria. So just how is that happening?
While customers are pushing back—filing complaints with their IP suppliers and foundry, and insisting that IP vendors implement more stringent DFM assurance processes—in today’s world, both designers and foundries often take matters into their own hands and run their own "DFM sanity checks" on IP before allowing it into designs. In fact, not only will they apply DFM validation to IP designs during design phases, they often produce test chips and examine the results in silicon.
But that’s a state of affairs that is unlikely to continue. As DFM optimization becomes a requirement at smaller nodes, IP vendors are going to have to collaborate with the foundries and EDA companies to implement and enforce IP DFM compliance and optimization.
When DFM first became a significant issue on designs starting at 65nm, forward-looking foundries and IP vendors recognized the importance of DFM-optimized IP to foundry design customers and began their own investigation into the development issues and potential solutions and methodologies. For example, the Common Platform Alliance (CP) and its member companies formed focus groups as early as 2005 to examine design issues related specifically to defect sensitivity and manufacturing variability. Because DFM was a constantly evolving set of requirements, the first steps were an attempt to define and delineate the issues that would be considered "DFM." Over time, those early investigations evolved into a range of specific activities, such as tool selection/ recommendation, process flow development/ review, documentation development and support for customer DFM activities.
It quickly became apparent that designers could not physically review every IP DFM issue and still produce end products in a timely and consistent manner. Tools that could provide automated recognition and analysis of these issues were needed. With the evolution of automated DFM optimization tools, continued progress was made toward IP DFM verification and enhancement on 65nm, 45nm, and most recently, 32nm. The results confirmed the value of the DFM compliance process, and enabled foundries and IP vendors to support end customers as they began implementing DFM on their own designs.
Out of the DFM research and development conducted by the foundries, several process flows and methodologies have been developed and are commonly used today. To enable automated DFM optimization, foundries are now providing the necessary DFM kits (specialized rules decks), and will suggest appropriate flows and methodologies. Examples of DFM kits that are currently available include critical feature and critical area analysis and optimization, lithography "hotspot" identification and optimization through the use of litho-friendly design (LFD) tools, and planarity and fill analysis and optimization through chemical-mechanical planarization (CMP) simulation and analysis.
Critical area analysis (CAA) is a well-established design process, intended to identify areas of designs that are susceptible to random defects during manufacture. By applying CAA to an IP design, IP vendors can provide assurance that the IP design has been built to avoid constructions that are particularly sensitive to the levels of random defects expected for a particular foundry process (see Figure 1).
Figure 1. Critical Area Analysis (CAA) characterizes the design susceptibility to random defects during manufacturing and helps prioritize various optimization techniques for each layer.
Recommended rules are defined in the design rule manual to add margin for various process effects (such as etch, stress, alignment, etc.). Critical feature analysis (CFA) kits help designers find, prioritize, and categorize high-impact recommended rule violations in a design. Using a CFA kit provides a significant benefit over traditional DRC alone. Even with the DFM recommended rule option turned on in the DRC, it would result in hundreds, if not thousands, of undifferentiated recommended rule violations, making it all but impossible to debug and correct the design in any practical timeline. However, by using the CFA kit, designers can use automated DFM tools to provide a prioritized list of high-impact recommended rule violations (see Figure 2).
Figure 2. Standard DRC checking provides no priority information about recommended rules violations, while a DFM deck used with a critical feature analysis tool such as Calibre YieldAnalyzer can prioritize and sort violations.
Lithography process variation is another significant DFM issue that is not adequately addressed by standard design tools or post-tapeout processing. Layout design does not currently quantify process window variations, while optical process correction (OPC) only corrects the design for the nominal lithographic process. To avoid potential lithographic issues very late in the design cycles, when fixes are extremely difficult, lithography simulation is used during the design and verification process. Lithography simulation tools use both RET (Reticle Enhancement Technology) and OPC information to predict silicon printed results, and also capture the process window (e.g., dose and focus) as shown in Figure 3.
Figure 3. Lithography simulation is based on production OPC/RET and also captures process window.
Not only does the use of lithography simulation allow IP vendors to uncover potential litho hotspots prior to actually applying OPC to the design, but its high accuracy provides the assurance needed to make its use both feasible and practical.
One other area of IC design now being addressed by DFM is that of planarity—the flatness of the IC after chemical-mechanical planarization. Designers have long used metal "fill" to achieve a more even distribution of metal across the die by adding non-functional metal shapes to "white space" regions in a design. One purpose of metal fill is to reduce the variations in thickness that occur during CMP. By achieving a more uniform thickness, designers can reduce variations in interconnect resistance. But the CMP impact on metal thickness also means the performance of the chip becomes more sensitive to parasitic capacitance (which is increased by adding metal fill) and variations in interconnect resistance. Meeting all of the manufacturing and performance constraints at 65nm and below requires accurate CMP simulation, better analysis to predict both the manufacturing and electrical impacts of fill, and more sophisticated algorithms that optimize the use of metal fill features. Figure 4 illustrates how planarity hotspots can be identified and optimized with automated CMP analysis tools.
Figure 4. Automated CMP analysis can identify and prioritize CMP hotspots, and automatically adjust fill to provide optimum planarity without compromising performance.
For standard cell designs, a fully automated DFM review process that includes automatic correction and optimization can be employed. In a fully automated process, the tools can not only automatically apply design corrections and enhancements that will improve DFM compliance, but they can also determine the optimal tradeoff point when there is an interaction or conflict between two interdependent design rules. Figure 5 illustrates one example of how this flow was applied to 45 nm standard cells and helped achieve substantial DFM improvements.
Figure 5. Results of automated DFM evaluation and enhancement for standard cells.
For more custom designs, such as leaf cells used in memory compilers, automated recognition and analysis of DFM design issues is required, but correction/ optimization of the custom design continues to be a manual process. DFM review with manual optimization is used at both 65nm and 45nm. After a design is DRC-clean, the IP vendor needs to perform DFM analysis. While physical DFM is the current focus, electrical DFM should also be applied. DFM issues identified during the DFM reviews can then be debugged and corrected manually by the designer. Figure 6 illustrates a sample workflow for a manual DFM IP optimization process:
Figure 6. Manual DFM flow for custom designs (e.g., memory leaf cells).
But it’s not enough just to perform internal DFM on IP. The IP vendors and foundries need to establish specifications and requirements (both in tools and processes) to define DFM quality levels, and then develop a means of communicating the results to the customers so they know 1) IP has been certified, and 2) precisely what that certification means. As an initial step in this process, some IP vendors have integrated the IP DFM validation with their on-going IP quality assurance (QA) process. The leading foundries are now starting to participate in this process with IP vendors, and making the information available to their customers. In this manner, customers can be assured that the IP has met foundry DFM specifications. Figure 7 shows one such process flow.
Figure 7. IP DFM certification flow.
To successfully produce designs at 65nm and below, designers must be sure all components of the design have been optimized to reduce the impact of manufacturing process variation. When some of those components are purchased from 3rd parties, designers want to be assured that those components have gone through a rigorous DFM verification process before being incorporated into the design.
The process of formalizing the techniques discussed in this article has already begun. Foundries and IP vendors are stepping up to the challenge of establishing the necessary protocols and certification processes needed to create and sustain a proven, accepted standard of IP DFM certification. In addition, DFM application notes provided by the foundries are beginning to contain suggested flows and methodologies, as well as acceptance criteria for the IP designers to reference.
As we progress from 65nm to 45nm, 32nm, and beyond, and the use of IP components becomes more pervasive, chip designers must continue to have confidence that the IP they bring into their designs has met the highest DFM standards for the applicable process. The establishment of golden DFM standards and methodologies is a critical step in making that assurance possible, and allowing the continued development of complex, high-performing chips at leading process nodes.
By David Abercrombie
David Abercrombie is the Program Manager for Advanced Physical Verification Methodology at Mentor Graphics, Wilsonville, OR. He has 15 years of experience leading yield enhancement programs in semiconductor manufacturing for Mentor Graphics and other companies, including LSI Logic, Motorola, Harris and General Electric. David received a BSEE degree from Clemson University and an MSEE degree from North Carolina State University.
Go to the Mentor Graphics Corp. website to learn more.