July 12, 2004 -- Verification reuse is critical to the productivity and efficiency of system-on-chip (SoC) verification. The foundation of this technique is well-designed verification codes and components that implement reusability techniques. Before developing the code, however, it is essential for the designer to learn practical, real-world techniques on how to create a highly reusable verification environment using an environment such as Specman e. Such a guide includes project management, testbench architecting, verification planning, test case creation and scripting.
By Steve Ye. (Ye is a senior engineer in the IP Reuse Design & Development group of Agere Systems.)
This brief introduction has been excerpted from the original copyrighted article.