February 12, 2007 -- This article formalizes the concept of best possible verification quality — completeness — and describes a methodology, field-proven on many complex module and intellectual property (IP) designs, that tells you when verification is complete. To demonstrate the results, it summarizes the verification of a protocol processor IP from Infineon.
How do you know when functional verification of IP is complete? Functional verification is complete when the IP's implemented behavior and specified behavior correspond with each other. At this point, the design is error-free.
But how do you know when that is? Is it when every line item in the verification plan is checked off? Is it when 100% of the RTL code is covered? Or is it when last week's verification runs have detected no further errors? And does achieving these "completeness" goals imply that the design is free of functional errors?
By Dr. Wolfram Buettner and Dr. Michael Siegel. (Buettner is Managing Director and Chief Technology Officer of OneSpin Solutions GmbH, and Siegel is Senior Manager, Product Development.)
This brief introduction has been excerpted from the original copyrighted article.
