Page loading . . .

  
 You are at: The item(s) you requested.Thursday, June 20, 2013
Verification Methodologies Keep Pace with Complex IP  
Publication: EE Times EDA Designline
Contributor: NXP Semiconductors
 Printer friendly
 E-Mail Item URL

August 14, 2007 -- The verification of IP cores continues getting more complex and time consuming, especially processor cores, such as CPUs, floating-point units, and digital signal processors, the subject of this story. The challenge is to design and verify a new embedded vector processor with significant enhancements over its predecessor. This has been achieved by NXP's Adelante VD3204x Embedded Vector DSP family.

In order to improve the quality of our DSP technology at DSP-IC, a department within NXP Semiconductors (formerly Philips Semiconductors), the attention for verification turned to tools and techniques that might advance the verification process. The experiences are shared in this artile.

By Roger Witlox, Ronald Heijmans and Chris Wieckardt (Witlox is Senior Verification Engineer at SiTel Semiconductor BV; Heijmans is a Senior Verification Engineer and Wieckardt is a Verification Engineer with NXP Semiconductors.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times EDA Designline website.

Read more about
NXP Semiconductors
on SOCcentral.com

Keywords: EE Times EDA Designline, NXP Semiconductors, DSP, digital signal processing, IP, intellectual property, cores, verification, EDA tools,
579/23725 8/14/2007 9571 538
Designer's Mall
4th Of July countdown banner
0.1719971



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options


Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Reducing Power
by Raising the
Level of Abstraction


David Pursley
Director,
Product Marketing
Forte Design Systems

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Summertime and the Livin' Ain't Easy


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL?


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.25