April 14, 2008 -- The rapid adoption of high-speed serial interconnect in recent years have posed new challenges to design engineers. Many embedded systems engineers are facing designs with PCIe and Serial Rapid I/O, and this trend will continue.
Design engineers must keep up with system bandwidth demands while maintaining compatibility with legacy line cards and attempting to support next-generation higher-bandwidth systems. The data rates of serial protocols are doubling and quadrupling, with PCI Express a prime example. Before the ink dried on the Gen 1.0 2.5-Gbps specification, work was underway on the Gen 2.0 specification for 5.0-Gbps serial data rate. Now, the standards body is defining 8.0-Gbps Gen 3.0. While many of these protocols share common physical layer and data link layers — differences appear in the upper layers of the protocol stack. The upper layers are geared to address specific needs of the application.
By Joel Martinez, Sridhar Krishnamurthy and Venkat YadavallI. (Martinez, Krishnamurthy and YadavallI are all with Altera Corp.)
This brief introduction has been excerpted from the original copyrighted article.
