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An Application Modeling and Hardware Description for Network-on-Chip Benchmarking  
Publication: EE Times Embedded
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January 14, 2009 -- Measuring and comparing performance, cost, and other features of advanced communication architectures for complex multicore/multiprocessor systems on chip is a significant challenge which has hardly been addressed so far.

The NoC Benchmarking Workgroup of OCP-IP presents a modeling concept for applications running on multicore systems and defines an XML format for documenting and distributing network-on-chip benchmarks.

It defines a black-box view of the processing elements that discloses only the computational aspects that are relevant in interacting with the on chip data transport mechanism. The purpose is to lay the groundwork for a standardized NoC benchmark set.

No optimal NoC exists in general case and a brute-force search is impossible due to vast design space. Benchmarking, however, allows identifying the most promising solutions which are then selected for detailed and more time consuming analysis.

This reduces the design time notably once the major characteristics and requirements of the system are known. Furthermore, common point of reference is required for detailed comparison of approaches. Hence, NoC benchmarking aims to answer two basic questions:
  • NoC developer: What gain does my novel feature bring? .
  • System integrator: Which NoC should I choose? How should I configure it?

By Erno Salminen, Cristian Grecu, Timo D. Hamalainen, and Andre Ivanov. (Salminen is a Research scientist, M.Sc. at the Tampere University of Technology, Finland; Grecu holds a PH.D. from the University of British Columbia; Hamalainen is Professor and Institute Vice President at Tampere University of Technology; Ivanov holds a PhD from McGill University, currently chairs the Computer Society Test Technology Council.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times Embedded website.

Keywords: EE Times Embedded, ASICs, ASIC design, Open Core Protocol, OCP, IP, intellectual property, cores, network-on-chip, NoC, on-chip interconnect,
590/27851 1/14/2009 7416 268


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