June 4, 2009 -- This article presents a motion compensation soft IP for H.264/AVC decoding based on the MoCHA architecture. The IP was designed in VHDL and validated by simulation and by prototyping on a Xilinx FPGA platform. This IP is able to decode H.264/AVC Main Profile Level 4 (HDTV 1080p) at 30 fps in real time at 82-MHz operating frequency. This throughput is reached by relying on a new efficient interpolation solution and a 3-D cache solution that provides, in average, 60% of memory bandwidth reduction. This is also the only known IP that implements the motion vector predictor fully in hardware. The IP is composed by three main modules that can be used independently in accordance to the video decoding system demands. The ASIC version was generated through standard cells synthesis for TSMC 0.18µm and uses 114K gates.

Bruno Zatt, Arnaldo Azevedo, Luciano Agostini, Altamiro Susin and Sergio Bampi. (Zatt, Agostini, Susin, and Bampi are with Federal University of Rio Grande do Sul, Brazil; Azevedo is with the Computer Engineering Laboratory, TU Delft, The Netherlands.)