June 29, 2009 -- Deep sub-nanometer designs are stressed with large process variability. SRAM-bits have the most aggressive design rules in the SOCs, and the most variability. A dual-rail solution offsets some of the variability at the cost of additional design efforts. Dual-rail solutions appear to be complex, but several area, power, and performance tradeoffs can be made to simplify the design.

Traditionally, the dual-rail feature for SOCs and SRAMs has been associated with dynamic power-reduction techniques. To use these techniques, chip designers run a part of the IC, called a voltage island, at a lower voltage than the rest of the device in order to reduce dynamic power when the performance requirement of that voltage island is not the primary goal. Similarly, memory designers run a part of the memory, called memory periphery, at a lower voltage than the SRAM-bit in order to reduce dynamic power when the performance requirement is not the primary concern. This technique allows both chip designers and memory designers to reduce active power while still achieving sufficient performance .

Vipin Tiwari. (Tiwari is Senior Product Marketing Manager for advanced technology nodes for Virage Logic, Inc.)