| Minimal Effort Chip Design Using IP Featured | Publication: Design & Reuse Contributor: Freescale Semiconductor, Inc.
| | |
April 14, 2011 -- In order to speed up design cycles and to reduce development costs, use of external IP is increasingly becoming more popular. However, this IP-based design is not free of considerable effort and saves only about half of the effort required to develop the IP internally. The concept of Intelligent Design Automation (IDA) is presented here which uses intelligent algorithms such as matchmaking algorithm, rating systems, fuzzy logic, and multi-criteria optimization. This article also presents the idea of IP Integration Automation, or I2A, tools. Much of the technology required for these concepts to become reality already exists in various forms and is in use for a different class of solutions.
By Aseem Gupta, Ph.D. (Gupta is with Freescale Semiconductor, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Design & Reuse website.
Read more about Freescale Semiconductor, Inc. on SOCcentral.com |
| | Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, IP, intellectual property, cores, Freescale Semiconductor, Design & Reuse,
| | 599/33675 4/14/2011 1831 158 | |
|
|
|
|
| | 0.15625 |
|
|
| Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054 | |
|
| | |
|
|
Subscribe to SOCcentral's SOC Explorer Newsletter and receive news, article, whitepaper, and product updates bi-weekly.
|
|
|
Exec Viewpoint
The Many Faces of Low-Power Verification
 Ghislain Kaiser CEO, Docea Power
|
|
Exec Viewpoint
Maximizing the Value of Your Internal IP
 Warren Savage CEO, IPextreme
|
|
|
|
Barbara's Bytes
So, Just What Is ESL
 Barbara Tuck Senior Editor, SOCcentral
|
|
|
|
|
|
|
|
| Design Center |
| Whitepapers & App Notes |
|
|
|
|
|
| Live and Archived Webcasts |
|
|
|
|
|
| Newsletters |
|
|
|
|
|
|
About SOCcentral.com
Sponsorship/Advertising Information
|
|
|