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Evatronix Releases USB 2.0 High-Speed PHY to Complement Its USB Offering  
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June 27, 2011 -- Evatronix SA today announced the introduction of a USB High-Speed PHY IP that will complement its long-existing suite of USB 2.0 Device and Host controllers. Evatronix USB 2.0 PHY has already been silicon proven and guarantees compliance with all relevant layers of USB specification for High, Full and Low Speeds.

"With the release of our USB 2.0 PHY we passed the next significant milestone in our strategy to offer complete front-to-back IP solutions," said Wojciech Sakowski, Evatronix CEO. "With over 10 years of experience in developing and supporting USB 2.0 solutions, we can now seamlessly assist our customers in all their development stages from architectural concept to tape-out."

The Evatronix USBHS-PHY is a complete mixed-signal transceiver macro-cell that implements the USB 2.0 Physical Layer for Host and Device applications. It is compliant with the UTMI+ specification.

The Evatronix USBHS-PHY features a built-in self test, self-calibration termination and pull-up resistors for seamless operation. It also supports regular 3.3-V analog and 1.8-V digital core supplies, both with 10% of voltage tolerance. Numerous other features enable designers to tailor the USBHS-PHY to the needs of a particular application.

Availability

The Evatronix USBHS-PHY logic macro is available now on the LFoundry 150-nm process with the possibility to port it to any technology node from 45nm to 180nm.

Go to the Evatronix SA website to find additional information.

E-mail Evatronix SA for more information.

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Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, IP, intellectual property, cores, Universal Serial Bus, USB, Evatronix,
600/34170 6/27/2011 878 131
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