Page loading . . .

  
 You are at: The item(s) you requested.Friday, March 27, 2015
Evatronix Releases USB 2.0 High-Speed PHY to Complement Its USB Offering  
 Printer friendly
 E-Mail Item URL

June 27, 2011 -- Evatronix SA today announced the introduction of a USB High-Speed PHY IP that will complement its long-existing suite of USB 2.0 Device and Host controllers. Evatronix USB 2.0 PHY has already been silicon proven and guarantees compliance with all relevant layers of USB specification for High, Full and Low Speeds.

"With the release of our USB 2.0 PHY we passed the next significant milestone in our strategy to offer complete front-to-back IP solutions," said Wojciech Sakowski, Evatronix CEO. "With over 10 years of experience in developing and supporting USB 2.0 solutions, we can now seamlessly assist our customers in all their development stages from architectural concept to tape-out."

The Evatronix USBHS-PHY is a complete mixed-signal transceiver macro-cell that implements the USB 2.0 Physical Layer for Host and Device applications. It is compliant with the UTMI+ specification.

The Evatronix USBHS-PHY features a built-in self test, self-calibration termination and pull-up resistors for seamless operation. It also supports regular 3.3-V analog and 1.8-V digital core supplies, both with 10% of voltage tolerance. Numerous other features enable designers to tailor the USBHS-PHY to the needs of a particular application.

Availability

The Evatronix USBHS-PHY logic macro is available now on the LFoundry 150-nm process with the possibility to port it to any technology node from 45nm to 180nm.

Go to the Evatronix SA website to find additional information.

E-mail Evatronix SA for more information.

Read more about
Evatronix SA
on SOCcentral.com


Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, IP, intellectual property, cores, Universal Serial Bus, USB, Evatronix,
600/34170 6/27/2011 832 121
Designer's Mall
0.53125



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Executive
Viewpoint

Verification Contortions


Dr. Lauro Rizzatti
Verification Consultant
Rizzatti, LLC

Real Talk

P2415: The New Power Standard for Unified Hardware Abstraction


Graham Bell
VP Marketing
Real Intent

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Tutorials, Whitepapers & App Notes
Archived Webcasts
Newsletters



About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.59375