July 1, 2011 -- Digital Blocks, Inc. today announced the DB9100 BitBLT/ 2D Graphics Engine synthesizable RTL Verilog IP Core family. The DB9100 Graphics Engine IP complements Digital Blocks' DB9000 family of TFT LCD Controller IP Cores providing a system-level solution to graphics display application development centered around ASIC, ASSP, and FPGA components.

The DB9100 BitBLT Graphics Engine provides 256 raster operations on 3 sources of frame buffer data for block transfers with an array of available bitmap and 2D graphics operations. The high-performance 2D Graphics Engine renders line, polygon, and polygon block fills.

The DB9100 family supports the AMBA AXI4, AXI, AHB, and Avalon Bus fabrics. The AXI4, AXI, and AHB fabrics support ASIC and ASSP design teams. The AXI4 supports Xilinx FPGAs. The Avalon supports Altera FPGAs. The DB9100 is tuned to the unique capabilities of each fabric to maximize capability and performance. The DB9100 also comes with a graphics API reference design.

Availability