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Analog Bits Low-Jitter LC Tank PLL IP Targets Ultra-High-End Networking, Cloud Computing SOCs  
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August 2, 2011 -- Analog Bits, Inc. today announced immediate availability of a new high-precision, low-jitter LC Tank PLL IP for system-on-chip (SOC) applications running at 100Gbps and above data-transfer rates. This new addition expands Analog Bits' clocking IP product line of PLLs which will now enable SOC designs for very high-end telecommunications and networking applications that are helping expand the cloud computing market.

Positioned for high-fidelity, low-jitter sampling and transmission applications, the new LC Tank PLL operates on less than 12mW while capable of providing multiphase clocks of up to 14GHz in a footprint smaller than 0.26mm².

"Extremely low jitter PLLs, such as Analog Bits' 300fs-class IP proved extremely critical to the design success of our 28-Gbps SerDes that is proving to be a differentiating device cost-effectively targeting 100Gigabit Ethernet applications," said Norman Young, Vice President of Engineering , Inphi Corp.

The new LC Tank PLL is silicon-proven in TSMC's 40-nm general-purpose (G) process and is actively being ported to the foundry's 28-nm node. It incorporates special process components, such as process-specific inductors, to achieve its very high precision.

"To achieve better than 300 femtoseconds (fs) performance is definitely a clocking IP milestone. Putting this in context, 300fs is the duration of a vibration of the atoms in an iodine molecule, and a femtosecond is to a second, what a second is to 31.7 million years," explains Mahesh Tirupattur, Executive Vice President, Analog Bits.

Go to the Analog Bits, Inc. website to find additional information.

E-mail Analog Bits, Inc. for more information.

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Keywords: ASICs, ASIC design, IP, intellectual property, cores, clocks, clocking, clock distribution, phase-locked loops, PLLs, Analog Bits,
600/34382 8/2/2011 553 90
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