September 26, 2011 -- Altera Corp. today announced the availability of the industry's first Serial RapidIO Gen2 FPGA-based solution, enabling improved bandwidth and link flexibility for next-generation 3G and 4G wireless basestation deployments. Altera inter-operated its RapidIO MegaCore Function IP core implemented in a Stratix IV GX FPGA with a Serial RapidIO Gen 2 switch from Integrated Device Technology, Inc. (IDT). Altera's proven Serial RapidIO Gen2 solution increases system bandwidth by providing a 20-Gbaud packet-based interconnect for linking radio cards, host processors and digital signal processors used in high-performance communications systems.
Altera worked closely with IDT to inter-operate its Serial RapidIO Gen2 IP core with IDT's 80HCPS1848 switch in x1 and x4 configurations from 5Gbaud up to 20Gbaud. IDT offers an extensive line of high-performance, low power, low-latency Serial RapidIO solutions and is the only vendor to offer a Serial RapidIO Gen2 switch.
Altera offers a complete system-level, integration-ready Serial RapidIO solution that includes a Serial RapidIO IP core, reference designs and hardware-development platforms. Altera's Serial RapidIO MegaCore Function is available now for download as part of Altera's design suite and is supported within Altera's Quartus II software version 11.0. The IP core is available as encrypted IP or as source code for complete user control.
Go to the Altera Corp. website to find additional information.