SOCcentral: Fraunhofer IIS Becomes Tensilica Authorized Design Center Partner (Tensilica, Inc. 34730)

You are at: The item(s) you requested.

Tuesday, May 21, 2013

Fraunhofer IIS Becomes Tensilica Authorized Design Center Partner

Printer friendly

E-Mail Item URL

September 27, 2011 -- Tensilica, Inc. today announced that Fraunhofer Institut fur Integrierte Schaltungen (Fraunhofer IIS) has joined Tensilica's Xtensions partner network and become an authorized design center. Fraunhofer IIS will support mutual customers with its audio-related SOC (system-on-chip) designs.

"Fraunhofer IIS is a valuable design center partner because of its domain knowledge and focus in audio signal-processing technology and receiver and broadcasting systems," stated Larry Przywara, Tensilica's Senior Director of Multimedia Marketing. "In particular, Fraunhofer has deep expertise in digital radio systems including DRM, DAB, satellite radio and DVB-SH, as well as audio-coding standards development including MP3, AAC and related MPEG codecs and post processing algorithms."

"We look forward to working closely with Tensilica and the wide customer base using Tensilica's HiFi Audio DSPs, especially for home entertainment, automotive and mobile multimedia," stated Marc Gayer, head of Embedded Audio at Fraunhofer IIS. "Tensilica's HiFi Audio DSP architecture is extremely efficient with industry best area and power requirements."

Go to the Tensilica, Inc. website to find additional information.

E-mail Tensilica, Inc. for more information.

Read more about
Tensilica, Inc.
and
Fraunhofer Institut fur Integrierte Schaltungen
on SOCcentral.com

Keywords: ASICs, ASIC design, IP, intellectual property, cores, microprocessors, MPUs, DSP, digital signal processing, digital signal processors, Tensilica, Fraunhofer Institut fur Integrierte Schaltungen, Fraunhofer IIS,

600/34730 9/27/2011 722 82

Designer's Mall

0.390625

Search site for:
Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP

Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship

Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!

Mike Donlin
The Write Solution
Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL

Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search
SOC Design ASIC Design ASIC Verification FPGA Design CPLD Design PCB Design DSP Design RTOS Development Digital Design	Analog Design Mixed-Signal Design DFT DFM IC Packaging VHDL Verilog SystemC SystemVerilog