December 12, 2011 -- Altera Corp. today announced it has successfully interoperated its 28-nm FPGA with PLX Technology, Inc.'s ExpressLane PCI Express (PCIe) Gen3 switch. Stratix V GX FPGAs feature hard PCIe Gen3 IP blocks and are the only FPGA shipping today that interoperate with a PCIe Gen3 switch.

"Interoperating the industry's highest-performance 28-nm FPGA with the industry's first PCIe Gen3 switch saves significant development time by enabling developers to focus on design issues rather than verifying electrical compliance between devices," said Patrick Dorsey, Senior Director of Component Marketing at Altera. "The hard PCIe Gen 3 IP blocks in Stratix V conserve logic resources, while increasing throughput and reducing power consumption for high-performance, leading-edge applications."

Stratix V FPGAs feature up to four hard PCIe Gen3 x8 IP blocks. The PCIe Gen3 IP blocks support x1, x2, x4 and x8 lane configurations and provide transfer rates up to 8Gbps per lane, sustaining 2X higher throughput using Gen3 x8 lanes compared to the previous Gen2 x8 version. Hardening the PCIe IP blocks in Stratix V FPGAs delivers a savings of over 100,000 logic elements when compared to alternative soft implementations. The hard PCIe Gen3 IP blocks embed the PCIe protocol stack into the FPGA and include the transceiver modules, physical layer, data link layer and transaction layer. Stratix V FPGA's PCIe Gen3 IP targets PCIe Base Specification Rev. 3.0, 2.x, and 1.x.

PCIe Gen3 is the latest version of the industry's most popular high-speed interconnect technology, and PLX switches blend valuable innovation and high port counts to enable new, more powerful designs in servers, storage and communications platforms. The PLX Gen3 portfolio includes 11 devices ranging from 12 to 48 lanes and three to 18 ports with more configurations in development. All devices are available today from PLX.

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