March 12, 2012 -- Cortus SA has announced the release of two bridges for their processor products. The first bridge is between the Cortus APS bus and AHB-Lite while the second bridge is between the APS bus and APB.

The Cortus family of processors are supported by the efficient, low-latency APS bus. This bus provides high-speed interfacing between the Cortus processors and synchronous SRAM. The bus is also supported by Cortus' family of peripherals. Nevertheless, many companies have existing investments in peripherals that use AHB or APB. Furthermore many older 32-bit processor cores make use of the AHB-Lite bus.

The new Cortus bridge products enable licensees of APS3 or FPS6 to cleanly interface to existing AHB & APB subsystems. Then new bridges also enable a smooth migration of existing subsystems based on older microcontroller cores to Cortus microcontroller cores.

"C and C++ rather than a particular instruction set are the industry standards for embedded systems," said Michael Chapman, CEO and President of Cortus. "All modern 32-bit cores support C and C++ and the main challenge to migrating designs lies in peripherals for which hardware-dependent software must be written. In modern system-on-chip applications there is virtually no processor-specific code. The new bridges will enable drop-in replacement of older cores by efficient Cortus ones, the main issue for licensees will be writing the interrupt handler."

The Cortus microcontroller core family includes the efficient APS3 and the high-performance FPS6 with further cores due for release later in 2012. According to Cortus, the APS3 offers the best performance in the industry in terms of DMIPS/mW and DMIPS/mm² and has been licensed for low-power applications such as Bluetooth LE, touchscreen controllers and SIM cards. The FPS6 provides high-throughput floating-point computation for applications such as motor control and floating-point signal processing.