March 26, 2012 -- Synopsys, Inc. today unveiled its initiative to accelerate the design of stacked multiple-die silicon systems using 3D-IC integration. As part of its 3D-IC initiative, Synopsys is working closely with leading IC design and manufacturing companies to deliver a comprehensive EDA solution, including enhanced versions of its IC-implementation and circuit-simulation products.

"As 2D scaling becomes impractical, 3D-IC integration becomes the natural evolution of semiconductor technology; it is the convergence of performance, power and functionality," said Phil Marcoux, Managing Director at PPM Associates. "Some of the benefits of 3D-IC integration, such as increasing complexity, improved performance, reducing power consumption and decreasing footprints, are proven and readily understood. Other reported benefits, such as improving time-to-market, lowering risk and lowering cost, still need to be realized before 3D-IC integration becomes a commercially viable alternative to traditional 2D architectures. The availability of Synopsys' silicon-proven EDA and IP solutions is an important contribution to deploying 3D-IC integration technology in the semiconductor industry."

Synopsys' 3D-IC initiative begins at the semiconductor device level. Multi-die stacks incorporate different materials, often bonded together, with varying coefficients of thermal expansion (CTE). Any temperature change causes material stress due to thermal mismatch, leading to silicon deformation and affecting transistor performance. Furthermore, TSVs, microbumps and other solder bumps produce a permanent stress in the zone around them. Synopsys' Sentaurus Interconnect TCAD tool analyzes these effects and models the TSVs in the die stacks, enabling performance and reliability optimization. Semiconductor companies, such as foundries, use modeling results to create design rules specific to 3D-IC integration to ensure manufacturability and reliability.

As part of its 3D-IC initiative, Synopsys is delivering a comprehensive EDA solution to enable design for 3D-IC integration:

DFTMAX test automation - design-for-test for stacked die and TSV. DesignWare STAR Memory System IP - integrated memory test, diagnostic and repair solution. IC Compiler - place-and-route support, including TSV, microbump, silicon interposer redistribution layer (RDL) and signal routing, power mesh creation and interconnect checks. StarRC Ultra parasitic extraction - support for TSV, microbump, interposer RDL and signal-routing metal. HSpice and CustomSim circuit simulation - multi-die interconnect analysis. PrimeRail - IR-drop and EM analysis. IC Validator - DRC for microbumps and TSVs, LVS connectivity checking between stacked die. Galaxy Custom Designer implementation solution - specialized custom edits to silicon interposer RDL, signal routing and power mesh. Sentaurus Interconnect - thermo-mechanical stress analysis to evaluate the impact of TSVs and microbumps used in multi-die stacks.

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