April 2, 2012 -- Open-Silicon, Inc. announced today version six of the company's Interlaken IP core. Networking, storage and high-performance computing products can benefit from the chip-to-chip interface speeds now enabled by the semiconductor industry's first Interlaken IP core to support up to 600-Gbps applications. This release offers implementation flexibility by supporting SerDes data rates up to 28Gbps and multiple data-width options. The IP core also conforms to the recently released "Interlaken Retransmit Extension" protocol definition from the Interlaken Alliance.

Open-Silicon's Interlaken IP provides a scalable, low-risk solution for the high-performance and reliability requirements of networking devices. Proven with silicon success in over 35 implementations, the updated version includes enhancements for increased configurability and flexibility. Customers can benefit from Open-Silicon's flexible business model, which allows them to license the IP alone or also take advantage of Open-Silicon's system and physical design services to speed their chips to market.

Open-Silicon Interlaken Controller IP Version 6 features

More about the Open-Silicon ASIC Interlaken IP core

Developed to incorporate of the benefits of the popular SPI4.2 and XUAI interfaces, Interlaken is a scalable protocol for chip-to-chip packet transfers. High–bandwidth applications, such as those required in networking devices, can utilize the Interlaken protocol to build on the channelization and per-channel flow control features, while reducing the number of chip I/O pins by using high-speed SerDes technology. Interlaken as a protocol has transitioned from the original chip-to-chip interconnect between the network processor and traffic manager to other applications like the extensions to support Interlaken Look Aside as the interconnect for external memory interfaces.

Open-Silicon's Interlaken IP can now scale from 10Gbps to over 600Gbps of bandwidth through the combination of SerDes speed (3.125Gbps to 28+Gbps) and a variable number of SerDes lanes (1 to 48). This scalability makes Open-Silicon Interlaken ideal for multiple generations of future network switches, routers and storage equipment.