May 29, 2012 -- Cadence Design Systems, Inc. today announced that its comprehensive suite of DDR controller and DDR PHY design IP, as well as its Cadence Verification IP Catalog, now support the latest release of the DFI specification, version 3.1. The new version adds support for the LPDDR3 mobile memory standard for smartphones and tablets, and includes enhancements to the PHY's low-power interface and training features.

"As the performance of the processors used in today's consumer electronics devices improves, so does their need for higher-bandwidth memory. The DFI interface standard was developed to give SOC designers a way to easily incorporate high-performance memory into their SOCs," said Marc Greenberg, Director of Marketing, SoC Realization, Cadence. "Through our close working relationship with the DFI Group, we are able to offer design and verification IP that supports the latest version of this popular interface standard."

About DFI 3.1

DFI 3.1 is a memory interface standard that enables the interoperability of IP between different companies. It defines methods for interfacing to DDR4 devices (with data rates up to 3.2Gbps per pin) and LPDDR3 devices (with data rates up 6.4Gbps. and 12.8Gbps for a dual channel configuration). The preliminary specification is available now for download at www.ddr-phy.org.