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Digital Core Design Introduces New Version of the Motorola 68000 16/32-bit MCU with Linux, MAC and Debugger  
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June 28, 2012 -- Digital Core Design (DCD) has introduced the D68000, the newest version of the Motorola 68000 16/32-bit microprocessor. The D68000 is a low-cost 32-bit MCU, offering not only a low-cost entry point but also effective performance. Improved architecture enables this IP core to run with uCLinux, so it can be easily used as for an HTTP server or FTP client.

The D68000 is 100% compatible with the original Motorola 68000. A test run on classic Amiga 500+ computer showed clearly that DCD's CPU can be 1:1 replacement for the original chip. But classic computers are not the target destination for the product. D68000 runs with uCLinux operating system, which makes this IP core a solution for embedded servers, certified to be used only with m68k processors. The BOA application is used as HTTP server and effective communication could be established through FTP protocol. uCLinux is a MMU-less derivative of the Linux operating system adopted for embedded solutions. It provides all of the Linux benefits including superior stability, common Linux kernel API, multitasking, full-featured TCP/IP networking, Virtual File System and reduces the amount of memory needed by its kernel and running applications.

New IP core is a technology-independent solution, which enables any engineer to implement it in Altera, Lattice or Xilinx technology. The D68000 is binary-compatible with m68k family of microprocessors. More over, the D68000 has a 16-bit data bus and a 24-bit address data bus. Its code is compatible with the MC68008, upward code-compatible with the MC68010 virtual extensions and the MC68020 32-bit implementation of the architecture. The improved instruction set allows program excecution with higher performance than the standard 68000 core can offer. MULS, MULU take just 28 clock periods, the same as DIVS, DIVU. Optimized shifts and rotations, combined with shorter effective-address-calculation time and removed idle cycles make this IP core much more power efficient.

To complement the D68000 offer, it's being developed with DoCD-BDM hardware debugger, which provides debugging capability not only for the IP core, but for the entire SOC system. DCD's debugger is 100% compatible with BDM debug interfaces, working smoothly with its interfaces/ cables: Public Domain cable, Macraigor Wiggler and P&E BDM cable. DoCD's also fully supported by standard debugging tools like GNU GD8 debugger, Cosmic ZAP debugger and Tasking debugger.

To make implementation process even easier DCD’s solution is delivered with fully automated test-bench and complete set of tests, which allow easy package validation at each stage of SOC design flow.

Key features

  • Software compatible with 68000 industry standard.
  • MULS, MULU take 28 clock periods.
  • DIVS, DIVU take 28 clock periods.
  • Optimized shifts and rotations.
  • Idle cycles removed to improve performance.
  • Shorter effective address calculation time.
  • Bus cycle timings identical to 68000.
  • 32-bit data and address registers.
  • 14 addressing modes.
  • 5 data types supported:
    • bits.
    • BCD.
    • bytes, words and long words.
  • Arithmetic Logic Unit includes:
    • 8,16,32-bit arithmetic and logical operations.
    • 16x16-bit signed and unsigned multiplication.
    • 32/16-bit signed and unsigned division.
    • Boolean operations.
  • Interrupt controller:
    • 7 priority levels interrupt controller.
    • Unlimited number of virtual interrupt sources.
    • Vectored and auto-vectored modes.
    Memory interface includes:
    • Up to 4GBytes of address space.
    • 16-bit data bus.
    • Asynchronous bus control.
  • M6800 family synchronous interface.
    • 3- and 2- wire bus arbitration.
    • Supervisor and user modes.
  • Fully synthesizable.
  • Static synchronous design.

Posted by: John Miklosz



Go to the Digital Core Design website to find additional information.

E-mail Digital Core Design for more information.

Read more about
Digital Core Design
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Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, IP, intellectual property, cores, 68000 microcontrollers, MCUs, Digital Core Design
601/38767 6/28/2012 484 75


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