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Enabling Error Resilience Throughout the Embedded System  
Publication: EE Times Programmable Logic Designline
Contributor: Altera Corp.
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July 10, 2012 -- Decreasing semiconductor device geometries allow ever higher levels of integration in system-on-chip (SOC) devices. In the domain of FPGAs, this results in very-high-capacity programmable hardware devices. At 28-nm, the latest trend in FPGAs is to combine FPGA fabric with a high-performance SOC. Dubbed an "SoC FPGA," these devices contain a dual-core ARM Cortex A9 processor, level 2 cache, a rich set of peripherals, up to four memory controllers, high-speed transceivers, and a low-power, low-cost 28-nm FPGA fabric. Such a concentration of computational performance drives embedded systems to carrying an abundance in memory capacity. Several gigabytes of DDR is no exception, and with that more attention must be paid to the probability and avoidance of soft errors.

By Hans Spanjaart. (Spanjaart is a Senior Technical Marketing Manager at Altera Corp. for SoC FPGA products.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times Programmable Logic Designline website.

Read more about
Altera Corp.
on SOCcentral.com

Keywords: FPGAs, field programmable gate arrays, FPGA design, IP, intellectual property, cores, ARM-based microprocessors, MPUs, EE Times Programmable Logic Designline, Altera,
602/38866 7/10/2012 799 77


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