Computational horsepower is always a concern for ASIC and SOC designers. I/O bandwidth is yet another. Configurable processor cores allow ASIC and SOC designers to add internal registers and function units that boost computational throughput, often by a factor of 10 to 100. However, increased computational performance places even more demand on the processor's I/O speed, to bring operands into the core and to ship results out. Conventional bus-centric design for on-chip I/O simply cannot handle the resulting increased traffic. Direct port I/O and FIFO queue interfaces can quickly ease the traffic load on overused buses, which greatly simplifies the design of complex chips.
Most processors, configurable or not, rely on one or a few buses to move data into and out of the processor core. These buses are increasingly inadequate for high-throughput applications such as video compression/decompression or high-speed networking. A new, configurable feature called "ports and queues," , based on tried-and-true system technology, provides the ASIC and SOC design team with as much bandwidth as any system can possibly use, essentially unlimited I/O bandwidth.
